yes i know, not supposed to do multi-purpose commit....
/*=======================*/
/*===== Import the slow peripherals ====*/
{0}
+ `ifdef CLINT
+ import clint::*;
+ `endif
+ `ifdef PLIC
+ import plic ::*;
+ `endif
`ifdef AXIEXP
import axiexpansion ::*;
`endif
- import pinmux::*;
- import mux::*;
- import gpio::*;
/*=====================================*/
/*===== interface declaration =====*/
method Bit#(`Reg_width) mtime;
`endif
`ifdef PLIC method ActionValue#(Tuple2#(Bool,Bool)) intrpt_note; `endif
- `ifdef I2C0 method Bit#(1) i2c0_isint; `endif
- `ifdef I2C1 method Bit#(1) i2c1_isint; `endif
- `ifdef QSPI0 method Bit#(1) qspi0_isint; `endif
- `ifdef QSPI1 method Bit#(1) qspi1_isint; `endif
- `ifdef UART0 method Bit#(1) uart0_intr; `endif
- // NEEL EDIT
interface IOCellSide iocell_side; // mandatory interface
- interface GPIO_config#(3) pad_configa; // depends on the number of banks
- // NEEL EDIT OVER
endinterface
/*================================*/
from bsv.wire_def import generic_io # special case
from bsv.wire_def import muxwire # special case
from ifacebase import InterfacesBase
+from bsv.peripheral_gen import PFactory
+slowfactory = PFactory()
class Pin(object):
self.pins = [] # a list of instances of class Pin
self.pinspecs = pinspecs # a list of dictionary
self.single = single
+ self.slow = None
+ slow = slowfactory.getcls(ifacename)
+ if slow:
+ self.slow = slow()
+
for p in pinspecs:
_p = {}
_p.update(p)
res = res.format(*args)
return '\n' + res + '\n'
+ def slowimport(self):
+ if not self.slow:
+ return ''
+ return self.slow.importfn().format()
+
+ def slowifdecl(self, count):
+ if not self.slow:
+ return ''
+ return self.slow.ifacedecl().format(count, self.ifacename)
+
class MuxInterface(Interface):
f.write(c.format(i))
f.write(self.data[name].wirefmt(i))
+ def slowimport(self, *args):
+ ret = []
+ for (name, count) in self.ifacecount:
+ ret.append(self.data[name].slowimport())
+ return '\n'.join(list(filter(None, ret)))
+
+ def slowifdecl(self, *args):
+ ret = []
+ for (name, count) in self.ifacecount:
+ for i in range(count):
+ ret.append(self.data[name].slowifdecl(i))
+ return '\n'.join(list(filter(None, ret)))
+
# ========= Interface declarations ================ #
class PBase(object):
pass
+
class uart(PBase):
def importfn(self):
return " import Uart16550 :: *;"
def ifacedecl(self):
- return " interface RS232_PHY_Ifc uart{0}_coe;" \
+ return " interface RS232_PHY_Ifc uart{0}_coe;\n" \
" method Bit#(1) uart{0}_intr;"
return " import I2C_top :: *;"
def ifacedecl(self):
- return " interface I2C_out i2c{0}_out;" \
+ return " interface I2C_out i2c{0}_out;\n" \
" method Bit#(1) i2c{0}_isint;"
return " import qspi :: *;"
def ifacedecl(self):
- return " interface QSPI_out qspi{0}_out;" \
+ return " interface QSPI_out qspi{0}_out;\n" \
" method Bit#(1) qspi{0}_isint;"
class gpio(PBase):
def importfn(self):
- return " import pinmux::*;" \
- " import mux::*;" \
- " import gpio::*;"
+ return " import pinmux::*;\n" \
+ " import mux::*;\n" \
+ " import gpio::*;\n"
def ifacedecl(self):
return " interface GPIO_config#({1}) pad_config{0};"
-
class PFactory(object):
- def __init__(self):
+ def getcls(self, name):
return {'uart': uart,
'rs232': rs232,
'twi': twi,
- 'qspi', qspi,
- 'pwm', pwm,
- 'gpio', 'gpio'
- }
+ 'qspi': qspi,
+ 'pwm': pwm,
+ 'gpio': gpio
+ }.get(name, None)
shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
os.path.join(bp, 'Makefile'))
cwd = os.path.join(cwd, 'bsv_lib')
- for fname in ['AXI4_Lite_Types.bsv', 'Semi_FIFOF.bsv',
- 'gpio.bsv', 'mux.bsv']:
+ for fname in ['AXI4_Lite_Types.bsv', 'Semi_FIFOF.bsv',
+ 'gpio.bsv', 'mux.bsv']:
shutil.copyfile(os.path.join(cwd, fname),
os.path.join(bl, fname))
ptp = os.path.join(bp, 'PinTop.bsv')
bvp = os.path.join(bp, 'bus.bsv')
idef = os.path.join(bp, 'instance_defines.bsv')
+ slow = os.path.join(bp, 'slow_peripherals.bsv')
+ slowt = os.path.join(cwd, 'slow_peripherals_template.bsv')
write_pmp(pmp, p, ifaces, iocells)
write_ptp(ptp, p, ifaces)
write_bvp(bvp, p, ifaces)
write_bus(bus, p, ifaces)
write_instances(idef, p, ifaces)
+ write_slow(slow, slowt, p, ifaces)
+
+
+def write_slow(slow, template, p, ifaces):
+ """ write out the slow_peripherals.bsv file.
+ joins all the peripherals together into one AXI Lite interface
+ """
+ with open(template) as bsv_file:
+ template = bsv_file.read()
+ imports = ifaces.slowimport()
+ ifdecl = ifaces.slowifdecl()
+ with open(slow, "w") as bsv_file:
+ bsv_file.write(template.format(imports, ifdecl))
def write_bus(bus, p, ifaces):
decl.append(muxdec .format(npins, bank))
idec.append(gpioifc.format(bank))
idec.append(muxifc.format(bank))
- print dir(ifaces)
- print ifaces.items()
- print dir(ifaces['gpioa'])
- print ifaces['gpioa'].pinspecs
+ print (dir(ifaces))
+ print (ifaces.items())
+ print (dir(ifaces['gpioa']))
+ print (ifaces['gpioa'].pinspecs)
gpiodecl = '\n'.join(decl) + '\n' + '\n'.join(idec)
gpiocfg = '\n'.join(cfg)
bsv_file.write(axi4_lite.format(gpiodecl, gpiocfg))
# ##################################################
-def write_instances(idef, p, ifaces):
+
+def write_instances(idef, p, ifaces):
with open(idef, 'w') as bsv_file:
txt = '''\
`define ADDR {0}
def __init__(self, iface):
self.pnames = []
for p in iface.pins:
- print "typ", p.typ, p.name
+ print ("typ", p.typ, p.name)
io = IO(p.typ, p.name)
setattr(self, p.name, io)
self.pnames.append(p.name)
- print dir(self)
+ print (dir(self))
def create_module(p, ifaces):
p.muxers.append(pin)
m = Mux(p.cell_bitwidth)
p.muxsel.append(m)
- print args
+ print (args)
p.myhdlifaces = []
for k, count in ifaces.ifacecount:
i = ifaces[k]
for c in range(count):
- print k
+ print (k)
args.append("%s%d" % (k, c))
p.myhdlifaces.append(MyHdlIface(ifaces[k]))
import sys
from spec import modules, specgen, dummytest
-from bsv.pinmux_generator import pinmuxgen as bsvgen
-from myhdlgen.pinmux_generator import pinmuxgen as myhdlgen
-
def printhelp():
print ('''pinmux_generator.py [-o outputdir] [-v|--validate] [-h|--help]
else:
specgen(of, output_dir, pinout, bankspec, pinspec, fixedpins)
else:
- gentypes = {'bsv': bsvgen, 'myhdl': myhdlgen}
- if output_type not in gentypes:
+ if output_type == 'bsv':
+ from bsv.pinmux_generator import pinmuxgen as gentypes
+ elif output_type == 'myhdl':
+ from myhdlgen.pinmux_generator import pinmuxgen as gentypes
+ else:
print ("ERROR: output type '%s' does not exist" % output_type)
printhelp()
sys.exit(0)
- gentypes[output_type](output_dir, validate)
+
+ gentypes(output_dir, validate)
projects / pinmux.git / commitdiff