quick addition of zero+immed test to LDSTCompUnit

diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py
index 85933a8889a0d2d94a3fe8e98a1f1aed10987d62..c3d2606a2083656ccbd2484d6d67ab8a86a007dd 100644 (file)
--- a/src/soc/experiment/compldst_multi.py
+++ b/src/soc/experiment/compldst_multi.py
@@ -541,23 +541,28 @@ def store(dut, src1, src2, src3, imm, imm_ok=True, update=False):
     return addr
 
 
-def load(dut, src1, src2, imm, imm_ok=True, update=False):
+def load(dut, src1, src2, imm, imm_ok=True, update=False, zero_a=False):
     print ("LD", src1, src2, imm, imm_ok, update)
     yield dut.oper_i.insn_type.eq(InternalOp.OP_LOAD)
     yield dut.src1_i.eq(src1)
     yield dut.src2_i.eq(src2)
+    yield dut.oper_i.zero_a.eq(zero_a)
     yield dut.oper_i.imm_data.imm.eq(imm)
     yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
     yield dut.issue_i.eq(1)
     yield
     yield dut.issue_i.eq(0)
     yield
-    if imm_ok:
-        yield dut.rd.go.eq(0b01)
-    else:
-        yield dut.rd.go.eq(0b11)
-    yield from wait_for(dut.rd.rel)
-    yield dut.rd.go.eq(0)
+    rd = 0b00
+    if not imm_ok:
+        rd |= 0b10
+    if not zero_a:
+        rd |= 0b01
+
+    if rd:
+        yield dut.rd.go.eq(rd)
+        yield from wait_for(dut.rd.rel)
+        yield dut.rd.go.eq(0)
 
     yield from wait_for(dut.adr_rel_o, False, test1st=True)
     #yield dut.ad.go.eq(1)
@@ -613,8 +618,14 @@ def scoreboard_sim(dut):
 
     # update-indexed version
     data, addr  = yield from load(dut, 4, 5, 0, imm_ok=False, update=True)
+    assert data == 0x0003, "returned %x" % data
     assert addr == 0x0009, "returned %x" % addr
 
+    # immediate *and* zero version
+    data, addr  = yield from load(dut, 4, 5, 9, imm_ok=True, zero_a=True)
+    assert data == 0x0003, "returned %x" % data
+
+
 class TestLDSTCompUnit(LDSTCompUnit):
 
     def __init__(self, rwid):