write-release moves out of "ALU valid" due to using alu_pulse

diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index 9810f3e06dbd2aca8cf7ed8d1019959384c1c006..e2a62f8a572c67163bfa1e320c374bd2f8990fda 100644 (file)
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -271,6 +271,10 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
         bro = Repl(self.busy_o, self.n_src)
         m.d.comb += self.rd.rel.eq(src_l.q & bro & slg) # src1/src2 req rel
 
+        # write-release gated by busy and by shadow
+        brd = Repl(self.busy_o & self.shadown_i, self.n_dst)
+        m.d.comb += self.wr.rel.eq(req_l.q & brd)
+
         # on a go_read, tell the ALU we're accepting data.
         # NOTE: this spells TROUBLE if the ALU isn't ready!
         # go_read is only valid for one clock!
@@ -281,8 +285,6 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
         brd = Repl(self.busy_o & self.shadown_i, self.n_dst)
         # only proceed if ALU says its output is valid
         with m.If(self.alu.n.valid_o):
-            # when ALU ready, write req release out. waits for shadow
-            m.d.comb += self.wr.rel.eq(req_l.q & brd)
             # when output latch is ready, and ALU says ready, accept ALU output
             with m.If(reset):
                 m.d.comb += self.alu.n.ready_i.eq(1) # tells ALU "got it"