interface GPIO#(numeric type ionum);
interface GPIO_config#(ionum) pad_config;
interface GPIO_func#(ionum) func;
- interface AXI4_Lite_Slave_IFC#(`ADDR,`DATA,`USERSPACE) axi_slave;
+ interface AXI4_Lite_Slave_IFC#(`PADDR,`DATA,`USERSPACE) axi_slave;
endinterface
module mkgpio(GPIO#(ionum_));
Vector#(ionum_,ConfigReg#(Bit#(1))) pwrupzhl_reg <-replicateM(mkConfigReg(0));
Vector#(ionum_,ConfigReg#(Bit#(1))) pwrup_pull_en_reg <-replicateM(mkConfigReg(0));
- AXI4_Lite_Slave_Xactor_IFC #(`ADDR, `DATA, `USERSPACE) s_xactor <- mkAXI4_Lite_Slave_Xactor;
+ AXI4_Lite_Slave_Xactor_IFC #(`PADDR, `DATA, `USERSPACE) s_xactor <- mkAXI4_Lite_Slave_Xactor;
rule rl_wr_respond;
// Get the wr request
let aw <- pop_o (s_xactor.o_wr_addr);
interface MUX#(numeric type ionum);
interface MUX_config#(ionum) mux_config;
- interface AXI4_Lite_Slave_IFC#(`ADDR,`DATA,`USERSPACE) axi_slave;
+ interface AXI4_Lite_Slave_IFC#(`PADDR,`DATA,`USERSPACE) axi_slave;
endinterface
// (*synthesize*)
module mkmux(MUX#(ionum_));
Vector#(ionum_,ConfigReg#(Bit#(2))) muxer_reg <-replicateM(mkConfigReg(0));
- AXI4_Lite_Slave_Xactor_IFC #(`ADDR, `DATA, `USERSPACE) s_xactor <- mkAXI4_Lite_Slave_Xactor;
+ AXI4_Lite_Slave_Xactor_IFC #(`PADDR, `DATA, `USERSPACE) s_xactor <- mkAXI4_Lite_Slave_Xactor;
let ionum=valueOf(ionum_);
rule rl_wr_respond;
// Get the wr request
import AXI4_Types::*;
interface Ifc_rgbttl_dummy;
- interface AXI4_Master_IFC#(`ADDR, `DATA, `USERSPACE) master;
- interface AXI4_Slave_IFC#(`ADDR, `DATA, `USERSPACE) slave;
+ interface AXI4_Master_IFC#(`PADDR, `DATA, `USERSPACE) master;
+ interface AXI4_Slave_IFC#(`PADDR, `DATA, `USERSPACE) slave;
interface Get#(Bit#(1)) de;
interface Get#(Bit#(1)) ck;
interface Get#(Bit#(1)) vs;
(*synthesize*)
module mkrgbttl_dummy(Ifc_rgbttl_dummy);
- AXI4_Slave_Xactor_IFC#(`ADDR,`DATA, `USERSPACE)
+ AXI4_Slave_Xactor_IFC#(`PADDR,`DATA, `USERSPACE)
s_xactor<-mkAXI4_Slave_Xactor();
- AXI4_Master_Xactor_IFC#(`ADDR,`DATA, `USERSPACE)
+ AXI4_Master_Xactor_IFC#(`PADDR,`DATA, `USERSPACE)
m_xactor<-mkAXI4_Master_Xactor();
Reg#(Bit#(1)) rg_de <- mkReg(0);
import AXI4_Lite_Types::*;
interface Ifc_sdcard_dummy;
- interface AXI4_Lite_Slave_IFC#(`ADDR, `DATA, `USERSPACE) slave;
+ interface AXI4_Lite_Slave_IFC#(`PADDR, `DATA, `USERSPACE) slave;
interface Get#(Bit#(1)) cmd;
interface Get#(Bit#(1)) clk;
interface Get#(Bit#(`SDBUSWIDTH)) out;
(*synthesize*)
module mksdcard_dummy(Ifc_sdcard_dummy);
- AXI4_Lite_Slave_Xactor_IFC#(`ADDR,`DATA, `USERSPACE)
+ AXI4_Lite_Slave_Xactor_IFC#(`PADDR,`DATA, `USERSPACE)
s_xactor<-mkAXI4_Lite_Slave_Xactor();
Reg#(Bit#(1)) rg_cmd <- mkReg(0);