remove default and swap over DIV/SQRT operations, to make SQRT the default

http://bugs.libre-riscv.org/show_bug.cgi?id=126

diff --git a/src/ieee754/div_rem_sqrt_rsqrt/core.py b/src/ieee754/div_rem_sqrt_rsqrt/core.py
index 507caf28e2abcaca1e2dfc9a0c28494b98e62697..cef62a343ad8da05d6c8746a30d8a276a050660f 100644 (file)
--- a/src/ieee754/div_rem_sqrt_rsqrt/core.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/core.py
@@ -59,8 +59,8 @@ class DivPipeCoreOperation(enum.Enum):
     :attribute RSqrtRem: reciprocal-square-root/remainder.
     """
 
-    UDivRem = 0
-    SqrtRem = 1
+    SqrtRem = 0
+    UDivRem = 1
     RSqrtRem = 2
 
     def __int__(self):

diff --git a/src/ieee754/fpdiv/div0.py b/src/ieee754/fpdiv/div0.py
index 7a39d72759bb24521788294533bb6006f0d0b67d..4b9f25a953e3c88dc8dd24a006f0179ebda4651b 100644 (file)
--- a/src/ieee754/fpdiv/div0.py
+++ b/src/ieee754/fpdiv/div0.py
@@ -88,9 +88,6 @@ class FPDivStage0Mod(Elaboratable):
                  self.o.divisor_radicand.eq(divr_rad),
         ]
 
-        # set default since it's not always set; non-zero value for debugging
-        comb += self.o.operation.eq(1)
-
         with m.If(~self.i.out_do_z):
             # DIV
             with m.If(self.i.ctx.op == int(DPCOp.UDivRem)):