TstL0CacheBuffer returns array of ports differently now

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index e52aac64079f2a3abba53b589e562de8172144a3..f19fe9f9959e90314b6622949d989c72bf8f5bb8 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -56,7 +56,7 @@ class NonProductionCore(Elaboratable):
     def __init__(self, addrwid=6, idepth=16):
         # single LD/ST funnel for memory access
         self.l0 = TstL0CacheBuffer(n_units=1, regwid=64, addrwid=addrwid)
-        pi = self.l0.l0.dports[0].pi
+        pi = self.l0.l0.dports[0]
 
         # function units (only one each)
         self.fus = AllFunctionUnits(pilist=[pi], addrwid=addrwid)