32-bit testing of output for CR0 conditions

diff --git a/src/soc/fu/alu/output_stage.py b/src/soc/fu/alu/output_stage.py
index c93fec5be47e8d04ba646a57292ef789f17e1cb0..20f00d6e55a875c1ac5eb4b6fcb20ad26f3dcbd0 100644 (file)
--- a/src/soc/fu/alu/output_stage.py
+++ b/src/soc/fu/alu/output_stage.py
@@ -21,14 +21,22 @@ class ALUOutputStage(PipeModBase):
     def elaborate(self, platform):
         m = Module()
         comb = m.d.comb
+        op = self.i.ctx.op
 
         # op requests inversion of the output
         o = Signal.like(self.i.o)
-        with m.If(self.i.ctx.op.invert_out):
+        with m.If(op.invert_out):
             comb += o.eq(~self.i.o)
         with m.Else():
             comb += o.eq(self.i.o)
 
+        # target register if 32-bit is only the 32 LSBs
+        target = Signal(64, reset_less=True)
+        with m.If(op.is_32bit):
+            comb += target.eq(o[:32])
+        with m.Else():
+            comb += target.eq(o)
+
         # create condition register cr0 and sticky-overflow
         is_zero = Signal(reset_less=True)
         is_positive = Signal(reset_less=True)
@@ -41,21 +49,21 @@ class ALUOutputStage(PipeModBase):
         # that can be used as a test
         # see https://bugs.libre-soc.org/show_bug.cgi?id=305#c60
 
-        comb += is_cmp.eq(self.i.ctx.op.insn_type == InternalOp.OP_CMP)
-        comb += msb_test.eq(o[-1] ^ is_cmp)
-        comb += is_zero.eq(o == 0)
+        comb += is_cmp.eq(op.insn_type == InternalOp.OP_CMP)
+        comb += msb_test.eq(target[-1] ^ is_cmp)
+        comb += is_zero.eq(target == 0)
         comb += is_positive.eq(~is_zero & ~msb_test)
         comb += is_negative.eq(~is_zero & msb_test)
         comb += so.eq(self.i.so | self.i.ov)
 
-        comb += self.o.o.eq(o)
-        with m.If(self.i.ctx.op.insn_type != InternalOp.OP_CMPEQB):
+        with m.If(op.insn_type != InternalOp.OP_CMPEQB):
             comb += self.o.cr0.eq(Cat(so, is_zero, is_positive, is_negative))
         with m.Else():
             comb += self.o.cr0.eq(self.i.cr0)
-            
-        comb += self.o.so.eq(so)
 
+        # copy [inverted] output, sticky-overflow and context out
+        comb += self.o.o.eq(o)
+        comb += self.o.so.eq(so)
         comb += self.o.ctx.eq(self.i.ctx)
 
         return m