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import error
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sat, 20 Jun 2020 11:02:07 +0000
(12:02 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sat, 20 Jun 2020 11:02:07 +0000
(12:02 +0100)
nmigen_soc/wishbone/sram.py
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diff --git
a/nmigen_soc/wishbone/sram.py
b/nmigen_soc/wishbone/sram.py
index ffb8f63da0c3a84cad1391deba5eeb363fdad8ef..030ad9073730e6fcb1e97b9b5c6f4b49f1c46936 100644
(file)
--- a/
nmigen_soc/wishbone/sram.py
+++ b/
nmigen_soc/wishbone/sram.py
@@
-1,7
+1,7
@@
from nmigen import Elaboratable, Memory, Module
from nmigen.utils import log2_int
-from nmigen.wishbone.bus import Interface
+from nmigen
_soc
.wishbone.bus import Interface
__all__ = ["SRAM"]