add a simple core, not intended for production use

diff --git a/src/soc/fu/compunits/compunits.py b/src/soc/fu/compunits/compunits.py
index 5f8ea2bd480bff9936937884a6ce331ad961ab9f..c8e4a2bcafcc834aa403177a2a70c5daed7c6c01 100644 (file)
--- a/src/soc/fu/compunits/compunits.py
+++ b/src/soc/fu/compunits/compunits.py
@@ -151,6 +151,7 @@ class AllFunctionUnits(Elaboratable):
     def ports(self):
         return list(self)
 
+
 def tst_single_fus_il():
     for (name, kls) in (('alu', ALUFunctionUnit),
                         ('cr', CRFunctionUnit),

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
new file mode 100644 (file)
index 0000000..ea26a0f
--- /dev/null
+++ b/src/soc/simple/core.py
@@ -0,0 +1,4 @@
+from nmigen import Elaboratable, Module
+
+from soc.fu.compunits.compunits import AllFunctionUnits
+from soc.regfile.regfiles import RegFiles