bit of whitespace

diff --git a/src/ieee754/part_cmp/experiments/eq_combiner.py b/src/ieee754/part_cmp/experiments/eq_combiner.py
index 21cd8b3e2d4fc1c6b321e200fcf2e303cad0a2ee..f3d299f780618a732debb32faa62221f20240068 100644 (file)
--- a/src/ieee754/part_cmp/experiments/eq_combiner.py
+++ b/src/ieee754/part_cmp/experiments/eq_combiner.py
@@ -2,14 +2,15 @@ from nmigen import Signal, Module, Elaboratable, Mux
 from ieee754.part_mul_add.partpoints import PartitionPoints
 
 
-
 class Twomux(Elaboratable):
+
     def __init__(self):
         self.ina = Signal()
         self.inb = Signal()
         self.sel = Signal()
         self.outa = Signal()
         self.outb = Signal()
+
     def elaborate(self, platform):
         m = Module()
         comb = m.d.comb
@@ -24,7 +25,9 @@ class Twomux(Elaboratable):
 #equals.py's giant switch statement. The idea is to use a tree of two
 #input/two output multiplexors and or gates to select whether each
 #signal is or isn't combined with its neighbors.
+
 class EQCombiner(Elaboratable):
+
     def __init__(self, width):
         self.width = width
         self.neqs = Signal(width, reset_less=True)
@@ -36,6 +39,7 @@ class EQCombiner(Elaboratable):
         comb = m.d.comb
 
         previnput = self.neqs[-1]
+
         for i in range(self.width-1, 0, -1): # counts down from width-1 to 1
             m.submodules["mux%d" % i] = mux = Twomux()
 

diff --git a/src/ieee754/part_cmp/experiments/gt_combiner.py b/src/ieee754/part_cmp/experiments/gt_combiner.py
index 06046fa2a182d1cfbcb3b1f73b4c2f1c165f763d..8be22dec3963d4eeb72d04c005149f6bee49e9b2 100644 (file)
--- a/src/ieee754/part_cmp/experiments/gt_combiner.py
+++ b/src/ieee754/part_cmp/experiments/gt_combiner.py
@@ -2,12 +2,14 @@ from nmigen import Signal, Module, Elaboratable, Mux
 from ieee754.part_mul_add.partpoints import PartitionPoints
 
 class Combiner(Elaboratable):
+
     def __init__(self):
         self.ina = Signal()
         self.inb = Signal()
         self.sel = Signal()
         self.outa = Signal()
         self.outb = Signal()
+
     def elaborate(self, platform):
         m = Module()
         comb = m.d.comb
@@ -25,7 +27,9 @@ class Combiner(Elaboratable):
 # partition's greater than flag is set, or the current partition's
 # equal flag is set AND the previous partition's greater than output
 # is true
+
 class GTCombiner(Elaboratable):
+
     def __init__(self, width):
         self.width = width
         self.mux_input = Signal(reset_less=True)  # right hand side mux input
@@ -39,6 +43,7 @@ class GTCombiner(Elaboratable):
         comb = m.d.comb
 
         previnput = self.gts[-1] | (self.eqs[-1] & self.mux_input)
+
         for i in range(self.width-1, 0, -1): # counts down from width-1 to 1
             m.submodules["mux%d" % i] = mux = Combiner()