Wire up missing CRG / DDR3 clock control / reset signals

diff --git a/src/ecp5_crg.py b/src/ecp5_crg.py
index 5c975d66c1dacaed906e13e96cb4781ceb64593a..b1bd03ce416778f4b49148023d93a2c22f5f879a 100644 (file)
--- a/src/ecp5_crg.py
+++ b/src/ecp5_crg.py
@@ -173,6 +173,10 @@ class ECP5CRG(Elaboratable):
         self.sys_clk_freq = sys_clk_freq
         self.pod_bits = pod_bits
 
+        # DDR clock control signals
+        self.ddr_clk_stop = Signal()
+        self.ddr_clk_reset = Signal()
+
     def elaborate(self, platform):
         m = Module()
 
@@ -204,16 +208,16 @@ class ECP5CRG(Elaboratable):
                              i_GSR=gsr1),
         ]
 
-        # PLL
-        m.submodules.pll = pll = PLL(ClockSignal("rawclk"), reset=~reset)
-
-        # Power-on delay (655us)
+        # Power-on delay
         podcnt = Signal(self.pod_bits, reset=-1)
         pod_done = Signal()
-        with m.If((podcnt != 0) & pll.locked):
+        with m.If(podcnt != 0):
             m.d.rawclk += podcnt.eq(podcnt-1)
         m.d.rawclk += pod_done.eq(podcnt == 0)
 
+        # PLL
+        m.submodules.pll = pll = PLL(ClockSignal("rawclk"), reset=~pod_done|~reset)
+
         # Generating sync2x (200Mhz) and init (25Mhz) from extclk
         cd_sync2x = ClockDomain("sync2x", local=False)
         cd_sync2x_unbuf = ClockDomain("sync2x_unbuf",
@@ -228,7 +232,7 @@ class ECP5CRG(Elaboratable):
         pll.create_clkout(ClockSignal("init"), 25e6)
         m.submodules += Instance("ECLKSYNCB",
                 i_ECLKI = ClockSignal("sync2x_unbuf"),
-                i_STOP  = 0,
+                i_STOP  = self.ddr_clk_stop,
                 o_ECLKO = ClockSignal("sync2x"))
         m.domains += cd_sync2x_unbuf
         m.domains += cd_sync2x
@@ -239,7 +243,7 @@ class ECP5CRG(Elaboratable):
         m.d.comb += reset_ok.eq(~pll.locked|~pod_done)
         m.d.comb += ResetSignal("init").eq(reset_ok)
         m.d.comb += ResetSignal("sync").eq(reset_ok)
-        m.d.comb += ResetSignal("dramsync").eq(reset_ok)
+        m.d.comb += ResetSignal("dramsync").eq(reset_ok|self.ddr_clk_reset)
 
         # # Generating sync (100Mhz) from sync2x
 
@@ -247,7 +251,7 @@ class ECP5CRG(Elaboratable):
             p_DIV="2.0",
             i_ALIGNWD=0,
             i_CLKI=ClockSignal("sync2x"),
-            i_RST=0,
+            i_RST=ResetSignal("dramsync"),
             o_CDIVX=ClockSignal("sync"))
 
         # temporarily set dram sync clock exactly equal to main sync

diff --git a/src/ls2.py b/src/ls2.py
index c4c63bca129361bedc058b52badbcaaad4db7cab..6cd644f42a7f4aeefb8df245ed243444e543242f 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -518,6 +518,10 @@ class DDR3SoC(SoC, Elaboratable):
             # grrr, same problem with drambone: not WB4-pipe compliant
             comb += drambone.bus.stall.eq(drambone.bus.cyc & ~drambone.bus.ack)
 
+            # DRAM clock control / reset signals
+            comb += self.crg.ddr_clk_stop.eq(self.ddrphy.init.stop)
+            comb += self.crg.ddr_clk_reset.eq(self.ddrphy.init.reset)
+
         # add hyperram module
         if hasattr(self, "hyperram"):
             m.submodules.hyperram = hyperram = self.hyperram