https://bugs.libre-soc.org/show_bug.cgi?id=446

Revert "LDSTSplitter: report exception"

This reverts commit 16f3cca9062314475a9039c96ffa1bc97122a408.

diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py
index 516c9c0c2f6dbb4c18ba459bf875bfefcfc2b5b6..3626b2e51ed95141d74cbb301641ab2a4803f682 100644 (file)
--- a/src/soc/experiment/pimem.py
+++ b/src/soc/experiment/pimem.py
@@ -105,7 +105,6 @@ class PortInterface(RecordObject):
         # addr is valid (TLB, L1 etc.)
         self.addr_ok_o = Signal(reset_less=True)
         self.addr_exc_o = Signal(reset_less=True)  # TODO, "type" of exception
-        self.exc_o = Signal(reset_less) # set by LDSTSplitter
 
         # LD/ST
         self.ld = Data(regwid, "ld_data_o")  # ok to be set by L0 Cache/Buf

diff --git a/src/soc/scoreboard/addr_split.py b/src/soc/scoreboard/addr_split.py
index c770c92e9a0739b23a0d046362724e2f6e4f8c80..aa99f63c9c097c2e8b5723f7b8ad899db857bcd9 100644 (file)
--- a/src/soc/scoreboard/addr_split.py
+++ b/src/soc/scoreboard/addr_split.py
@@ -78,7 +78,7 @@ class LDSTSplitter(Elaboratable):
         self.ld_data_o = LDData(dwidth, "ld_data_o") #port.ld
         self.st_data_i = LDData(dwidth, "st_data_i") #port.st
 
-        self.exc = pi.exc_o
+        self.exc = Signal(reset_less=True) # pi.exc TODO
 
         # TODO : create/connect two outgoing port interfaces