new fast3 needs to be remapped to fast1 port in "reduced ports" case in core

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index b5fbbebe559b08843967fc22175288424835c7a0..18d62ebac11d689cd6acbe1c03cba96a19659a43 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -365,6 +365,8 @@ class NonProductionCore(Elaboratable):
                     fuspecs['fast1'] = [fuspecs.pop('fast1')]
                     if 'fast2' in fuspecs:
                         fuspecs['fast1'].append(fuspecs.pop('fast2'))
+                    if 'fast3' in fuspecs:
+                        fuspecs['fast1'].append(fuspecs.pop('fast3'))
 
             # for each named regfile port, connect up all FUs to that port
             for (regname, fspec) in sort_fuspecs(fuspecs):
@@ -491,6 +493,8 @@ class NonProductionCore(Elaboratable):
                     fuspecs['fast1'] = [fuspecs.pop('fast1')]
                     if 'fast2' in fuspecs:
                         fuspecs['fast1'].append(fuspecs.pop('fast2'))
+                    if 'fast3' in fuspecs:
+                        fuspecs['fast1'].append(fuspecs.pop('fast3'))
 
             for (regname, fspec) in sort_fuspecs(fuspecs):
                 self.connect_wrport(m, fu_bitdict, wrpickers,