increase time for power-on-delay to 2^25 in ECP5

diff --git a/src/crg.py b/src/crg.py
index af2ccb1ea04909dfe44ae5bdbf955a74030b7052..a5370b78010a176602527206fdef92080415844f 100644 (file)
--- a/src/crg.py
+++ b/src/crg.py
@@ -206,7 +206,7 @@ class ECPIX5CRG(Elaboratable):
         m.submodules.pll = pll = PLL(ClockSignal("rawclk"), reset=~reset)
 
         # Power-on delay (655us)
-        podcnt = Signal(23, reset=-1)
+        podcnt = Signal(25, reset=-1)
         pod_done = Signal()
         with m.If((podcnt != 0) & pll.locked):
             m.d.rawclk += podcnt.eq(podcnt-1)