add jtag mkslow (actually, fast)

diff --git a/src/bsv/bsv_lib/soc_template.bsv b/src/bsv/bsv_lib/soc_template.bsv
index 834e967eca6c2d138c369f1291591a0b894fb1bc..5c27099e8a6ba25044717fc28a27aafa267da30e 100644 (file)
--- a/src/bsv/bsv_lib/soc_template.bsv
+++ b/src/bsv/bsv_lib/soc_template.bsv
@@ -113,7 +113,7 @@ package Soc;
         `ifdef FlexBus
             interface FlexBus_Master_IFC flexbus_out;
         `endif
-
+{1}
        endinterface
        (*synthesize*)
        module mkSoc #(Bit#(`VADDR) reset_vector, Clock slow_clock, Reset slow_reset, Clock uart_clock, 
@@ -121,6 +121,7 @@ package Soc;
                  `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc);
                Clock core_clock <-exposeCurrentClock; // slow peripheral clock
                Reset core_reset <-exposeCurrentReset; // slow peripheral reset
+{2}
       `ifdef Debug 
                        Ifc_jtagdtm tap <-mkjtagdtm(clocked_by tck, reset_by trst);
          rule drive_tmp_scan_outs;

diff --git a/src/bsv/peripheral_gen/base.py b/src/bsv/peripheral_gen/base.py
index 0d4384b1c25752a2a107164354b67698df37098b..a8e15f39c3cbed60d8feaf498a1b3e3ce3357561 100644 (file)
--- a/src/bsv/peripheral_gen/base.py
+++ b/src/bsv/peripheral_gen/base.py
@@ -270,7 +270,7 @@ class PeripheralIface(object):
 
 class PeripheralInterfaces(object):
     def __init__(self):
-        pass
+        self.fastbusmode = False
 
     def slowimport(self, *args):
         ret = []
@@ -432,7 +432,10 @@ class PeripheralInterfaces(object):
         return "    `define NUM_SLOW_IRQS {0}".format(self.num_slow_irqs)
 
     def is_on_fastbus(self, name, i):
+        #print "fastbus mode", self.fastbusmode, name, i
         iname = self.data[name].iname().format(i)
+        if self.fastbusmode:
+            return iname not in self.fastbus
         return iname in self.fastbus
 
 

diff --git a/src/bsv/peripheral_gen/jtag.py b/src/bsv/peripheral_gen/jtag.py
index 7f6a042e00d37fdd8c4be27ff37a29aec740240b..1f381f4e524cc2c01b5cadc4aff2195ac9da087f 100644 (file)
--- a/src/bsv/peripheral_gen/jtag.py
+++ b/src/bsv/peripheral_gen/jtag.py
@@ -6,6 +6,17 @@ class jtag(PBase):
     def slowimport(self):
         return "    import jtagtdm::*;\n"
 
+    def mkslow_peripheral(self):
+        return """\
+            Ifc_jtagdtm {0} <-mkjtagdtm(clocked_by tck, reset_by trst);
+         rule drive_tmp_scan_outs;
+             {0}.scan_out_1_i(1'b0);
+             {0}.scan_out_2_i(1'b0);
+             {0}.scan_out_3_i(1'b0);
+             {0}.scan_out_4_i(1'b0);
+             {0}.scan_out_5_i(1'b0);
+         endrule
+"""
     def axi_slave_name(self, name, ifacenum):
         return ''
 

diff --git a/src/bsv/pinmux_generator.py b/src/bsv/pinmux_generator.py
index 250d0ebe80e3322a1d60a86bd56b891704e8857c..c4f675ca217309c53692c69b1646b66bd092687e 100644 (file)
--- a/src/bsv/pinmux_generator.py
+++ b/src/bsv/pinmux_generator.py
@@ -128,14 +128,15 @@ def write_soc(soc, soct, p, ifaces, iocells):
     """ write out the soc.bsv file.
         joins all the peripherals together as AXI Masters
     """
+    ifaces.fastbusmode = True # side-effects... shouldn't really do this
     with open(soct) as bsv_file:
         soct = bsv_file.read()
     imports = ifaces.slowimport()
-    ifdecl = ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
+    ifdecl = "" #ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
     regdef = ifaces.axi_reg_def()
     slavedecl = ifaces.axi_slave_idx()
     fnaddrmap = ifaces.axi_addr_map()
-    mkslow = ifaces.mkslow_peripheral()
+    mkfast = ifaces.mkslow_peripheral()
     mkcon = ifaces.mk_connection()
     mkcellcon = ifaces.mk_cellconn()
     pincon = ifaces.mk_pincon()
@@ -145,10 +146,12 @@ def write_soc(soc, soct, p, ifaces, iocells):
     ifacedef = ifaces.mk_ext_ifacedef()
     ifacedef = ifaces.mk_ext_ifacedef()
     with open(soc, "w") as bsv_file:
-        bsv_file.write(soct.format(imports, ))#ifdecl, regdef, slavedecl,
-                                    #fnaddrmap, mkslow, mkcon, mkcellcon,
-                                    #pincon, inst, mkplic,
-                                    #numsloirqs, ifacedef))
+        bsv_file.write(soct.format(imports, ifdecl, mkfast,
+                            #'', '' #regdef, slavedecl,
+                            #'', mkslow, #fnaddrmap, mkslow, mkcon, mkcellcon,
+                            #pincon, inst, mkplic,
+                            #numsloirqs, ifacedef))
+                                  ))
 
 
 def write_bus(bus, p, ifaces):