got test_add.py running, with fpadd_state.py

diff --git a/src/ieee754/fcvt/test/test_fcvt_pipe.py b/src/ieee754/fcvt/test/test_fcvt_pipe.py
index 2036250659982ce6a4ac3474c73b5289f27fa51f..ee5ed3a5b25f38e9dc5005a440f5db7b5a72373f 100644 (file)
--- a/src/ieee754/fcvt/test/test_fcvt_pipe.py
+++ b/src/ieee754/fcvt/test/test_fcvt_pipe.py
@@ -6,17 +6,26 @@ from ieee754.fpcommon.test.fpmux import runfp
 
 from sfpy import Float64, Float32, Float16
 
-def fcvt_32_16(x):
+def fcvt_16(x):
     return Float16(x)
 
+def fcvt_32(x):
+    return Float32(x)
+
 def test_pipe_fp32_16():
     dut = FPCVTMuxInOut(32, 16, 4)
-    runfp(dut, 32, "test_fcvt_pipe_fp32_16", Float32, fcvt_32_16, True)
+    runfp(dut, 32, "test_fcvt_pipe_fp32_16", Float32, fcvt_16, True)
+
+def test_pipe_fp64_16():
+    dut = FPCVTMuxInOut(64, 16, 4)
+    runfp(dut, 64, "test_fcvt_pipe_fp64_16", Float64, fcvt_16, True)
 
-def test_pipe_fp64():
-    dut = FPCVTMuxInOut(64, 4)
-    runfp(dut, 64, "test_fcvt_pipe_fp64", Float64, mul, True)
+def test_pipe_fp64_32():
+    dut = FPCVTMuxInOut(64, 32, 4)
+    runfp(dut, 64, "test_fcvt_pipe_fp64_32", Float64, fcvt_32, True)
 
 if __name__ == '__main__':
+    test_pipe_fp64_16()
     test_pipe_fp32_16()
+    test_pipe_fp64_32()
 

diff --git a/src/ieee754/fpadd/fadd_state.py b/src/ieee754/fpadd/fadd_state.py
index 3a69bed7f436d0180597f8407afc2374fce0eb3b..7e978f5fa9c6ea0c139427037b2b71b970058c2c 100644 (file)
--- a/src/ieee754/fpadd/fadd_state.py
+++ b/src/ieee754/fpadd/fadd_state.py
@@ -6,7 +6,8 @@ from nmigen import Module, Signal, Cat, Elaboratable
 from nmigen.cli import main, verilog
 
 from ieee754.fpcommon.fpbase import (FPNumIn, FPNumOut, FPOpIn,
-                                     FPOpOut, Overflow, FPBase)
+                                     FPOpOut, Overflow, FPBase,
+                                     FPNumBaseRecord)
 
 from nmutil.nmoperator import eq
 
@@ -31,16 +32,16 @@ class FPADD(FPBase, Elaboratable):
         m = Module()
 
         # Latches
-        a = FPNumIn(self.in_a, self.width)
-        b = FPNumIn(self.in_b, self.width)
-        z = FPNumOut(self.width, False)
+        a = FPNumBaseRecord(self.width, False)
+        b = FPNumBaseRecord(self.width, False)
+        z = FPNumBaseRecord(self.width, False)
+        a = FPNumIn(None, a)
+        b = FPNumIn(None, b)
+        z = FPNumOut(z)
 
         m.submodules.fpnum_a = a
         m.submodules.fpnum_b = b
         m.submodules.fpnum_z = z
-        m.submodules.fpnum_in_a = self.in_a
-        m.submodules.fpnum_in_b = self.in_b
-        m.submodules.fpnum_out_z = self.out_z
 
         m.d.comb += a.v.eq(self.in_a.v)
         m.d.comb += b.v.eq(self.in_b.v)
@@ -50,8 +51,6 @@ class FPADD(FPBase, Elaboratable):
 
         of = Overflow()
 
-        m.submodules.overflow = of
-
         with m.FSM() as fsm:
 
             # ******

diff --git a/src/ieee754/fpadd/test/test_add.py b/src/ieee754/fpadd/test/test_add.py
index eadc94b182321857706516fe0a3b56fe8891324d..a53724379beb083e8e3a10bff3822ded4fcb3f9e 100644 (file)
--- a/src/ieee754/fpadd/test/test_add.py
+++ b/src/ieee754/fpadd/test/test_add.py
@@ -3,59 +3,59 @@ from operator import add
 from nmigen import Module, Signal
 from nmigen.compat.sim import run_simulation
 
-from ieee754.fpadd.nmigen_add_experiment import FPADD
+from ieee754.fpadd.fadd_state import FPADD
 
 from ieee754.fpcommon.test.unit_test_single import (get_mantissa, get_exponent,
                                 get_sign, is_nan,
                                 is_inf, is_pos_inf, is_neg_inf,
-                                match, get_rs_case, check_rs_case, run_fpunit,
+                                match, get_case, check_case, run_fpunit,
                                 run_edge_cases, run_corner_cases)
 
 def tbench(dut, maxcount, num_loops):
-    yield from check_rs_case(dut, 0x36093399, 0x7f6a12f1, 0x7f6a12f1)
-    yield from check_rs_case(dut, 0x006CE3EE, 0x806CE3EC, 0x00000002)
-    yield from check_rs_case(dut, 0x00000047, 0x80000048, 0x80000001)
-    yield from check_rs_case(dut, 0x000116C2, 0x8001170A, 0x80000048)
-    yield from check_rs_case(dut, 0x7ed01f25, 0xff559e2c, 0xfedb1d33)
-    yield from check_rs_case(dut, 0, 0, 0)
-    yield from check_rs_case(dut, 0xFFFFFFFF, 0xC63B800A, 0x7FC00000)
-    yield from check_rs_case(dut, 0xFF800000, 0x7F800000, 0x7FC00000)
-    #yield from check_rs_case(dut, 0xFF800000, 0x7F800000, 0x7FC00000)
-    yield from check_rs_case(dut, 0x7F800000, 0xFF800000, 0x7FC00000)
-    yield from check_rs_case(dut, 0x42540000, 0xC2540000, 0x00000000)
-    yield from check_rs_case(dut, 0xC2540000, 0x42540000, 0x00000000)
-    yield from check_rs_case(dut, 0xfe34f995, 0xff5d59ad, 0xff800000)
-    yield from check_rs_case(dut, 0x82471f51, 0x243985f, 0x801c3790)
-    yield from check_rs_case(dut, 0x40000000, 0xc0000000, 0x00000000)
-    yield from check_rs_case(dut, 0x3F800000, 0x40000000, 0x40400000)
-    yield from check_rs_case(dut, 0x40000000, 0x3F800000, 0x40400000)
-    yield from check_rs_case(dut, 0x447A0000, 0x4488B000, 0x4502D800)
-    yield from check_rs_case(dut, 0x463B800A, 0x42BA8A3D, 0x463CF51E)
-    yield from check_rs_case(dut, 0x42BA8A3D, 0x463B800A, 0x463CF51E)
-    yield from check_rs_case(dut, 0x463B800A, 0xC2BA8A3D, 0x463A0AF6)
-    yield from check_rs_case(dut, 0xC2BA8A3D, 0x463B800A, 0x463A0AF6)
-    yield from check_rs_case(dut, 0xC63B800A, 0x42BA8A3D, 0xC63A0AF6)
-    yield from check_rs_case(dut, 0x42BA8A3D, 0xC63B800A, 0xC63A0AF6)
-    yield from check_rs_case(dut, 0x7F800000, 0x00000000, 0x7F800000)
-    yield from check_rs_case(dut, 0x00000000, 0x7F800000, 0x7F800000)
-    yield from check_rs_case(dut, 0xFF800000, 0x00000000, 0xFF800000)
-    yield from check_rs_case(dut, 0x00000000, 0xFF800000, 0xFF800000)
-    yield from check_rs_case(dut, 0x7F800000, 0x7F800000, 0x7F800000)
-    yield from check_rs_case(dut, 0xFF800000, 0xFF800000, 0xFF800000)
-    yield from check_rs_case(dut, 0xFF800000, 0x7F800000, 0x7FC00000)
-    yield from check_rs_case(dut, 0x00018643, 0x00FA72A4, 0x00FBF8E7)
-    yield from check_rs_case(dut, 0x001A2239, 0x00FA72A4, 0x010A4A6E)
-    yield from check_rs_case(dut, 0x3F7FFFFE, 0x3F7FFFFE, 0x3FFFFFFE)
-    yield from check_rs_case(dut, 0x7EFFFFEE, 0x7EFFFFEE, 0x7F7FFFEE)
-    yield from check_rs_case(dut, 0x7F7FFFEE, 0xFEFFFFEE, 0x7EFFFFEE)
-    yield from check_rs_case(dut, 0x7F7FFFEE, 0x756CA884, 0x7F7FFFFD)
-    yield from check_rs_case(dut, 0x7F7FFFEE, 0x758A0CF8, 0x7F7FFFFF)
-    yield from check_rs_case(dut, 0x42500000, 0x51A7A358, 0x51A7A358)
-    yield from check_rs_case(dut, 0x51A7A358, 0x42500000, 0x51A7A358)
-    yield from check_rs_case(dut, 0x4E5693A4, 0x42500000, 0x4E5693A5)
-    yield from check_rs_case(dut, 0x42500000, 0x4E5693A4, 0x4E5693A5)
-    #yield from check_rs_case(dut, 1, 0, 1)
-    #yield from check_rs_case(dut, 1, 1, 1)
+    yield from check_case(dut, 0x36093399, 0x7f6a12f1, 0x7f6a12f1)
+    yield from check_case(dut, 0x006CE3EE, 0x806CE3EC, 0x00000002)
+    yield from check_case(dut, 0x00000047, 0x80000048, 0x80000001)
+    yield from check_case(dut, 0x000116C2, 0x8001170A, 0x80000048)
+    yield from check_case(dut, 0x7ed01f25, 0xff559e2c, 0xfedb1d33)
+    yield from check_case(dut, 0, 0, 0)
+    yield from check_case(dut, 0xFFFFFFFF, 0xC63B800A, 0x7FC00000)
+    yield from check_case(dut, 0xFF800000, 0x7F800000, 0x7FC00000)
+    #yield from check_case(dut, 0xFF800000, 0x7F800000, 0x7FC00000)
+    yield from check_case(dut, 0x7F800000, 0xFF800000, 0x7FC00000)
+    yield from check_case(dut, 0x42540000, 0xC2540000, 0x00000000)
+    yield from check_case(dut, 0xC2540000, 0x42540000, 0x00000000)
+    yield from check_case(dut, 0xfe34f995, 0xff5d59ad, 0xff800000)
+    yield from check_case(dut, 0x82471f51, 0x243985f, 0x801c3790)
+    yield from check_case(dut, 0x40000000, 0xc0000000, 0x00000000)
+    yield from check_case(dut, 0x3F800000, 0x40000000, 0x40400000)
+    yield from check_case(dut, 0x40000000, 0x3F800000, 0x40400000)
+    yield from check_case(dut, 0x447A0000, 0x4488B000, 0x4502D800)
+    yield from check_case(dut, 0x463B800A, 0x42BA8A3D, 0x463CF51E)
+    yield from check_case(dut, 0x42BA8A3D, 0x463B800A, 0x463CF51E)
+    yield from check_case(dut, 0x463B800A, 0xC2BA8A3D, 0x463A0AF6)
+    yield from check_case(dut, 0xC2BA8A3D, 0x463B800A, 0x463A0AF6)
+    yield from check_case(dut, 0xC63B800A, 0x42BA8A3D, 0xC63A0AF6)
+    yield from check_case(dut, 0x42BA8A3D, 0xC63B800A, 0xC63A0AF6)
+    yield from check_case(dut, 0x7F800000, 0x00000000, 0x7F800000)
+    yield from check_case(dut, 0x00000000, 0x7F800000, 0x7F800000)
+    yield from check_case(dut, 0xFF800000, 0x00000000, 0xFF800000)
+    yield from check_case(dut, 0x00000000, 0xFF800000, 0xFF800000)
+    yield from check_case(dut, 0x7F800000, 0x7F800000, 0x7F800000)
+    yield from check_case(dut, 0xFF800000, 0xFF800000, 0xFF800000)
+    yield from check_case(dut, 0xFF800000, 0x7F800000, 0x7FC00000)
+    yield from check_case(dut, 0x00018643, 0x00FA72A4, 0x00FBF8E7)
+    yield from check_case(dut, 0x001A2239, 0x00FA72A4, 0x010A4A6E)
+    yield from check_case(dut, 0x3F7FFFFE, 0x3F7FFFFE, 0x3FFFFFFE)
+    yield from check_case(dut, 0x7EFFFFEE, 0x7EFFFFEE, 0x7F7FFFEE)
+    yield from check_case(dut, 0x7F7FFFEE, 0xFEFFFFEE, 0x7EFFFFEE)
+    yield from check_case(dut, 0x7F7FFFEE, 0x756CA884, 0x7F7FFFFD)
+    yield from check_case(dut, 0x7F7FFFEE, 0x758A0CF8, 0x7F7FFFFF)
+    yield from check_case(dut, 0x42500000, 0x51A7A358, 0x51A7A358)
+    yield from check_case(dut, 0x51A7A358, 0x42500000, 0x51A7A358)
+    yield from check_case(dut, 0x4E5693A4, 0x42500000, 0x4E5693A5)
+    yield from check_case(dut, 0x42500000, 0x4E5693A4, 0x4E5693A5)
+    #yield from check_case(dut, 1, 0, 1)
+    #yield from check_case(dut, 1, 1, 1)
 
     count = 0
 
@@ -66,15 +66,15 @@ def tbench(dut, maxcount, num_loops):
     stimulus_b = [0xff800001, 0xadd79efa, 0xC0000000, 0x1c800000,
                   0xc038ed3a, 0xb328cd45, 
                     0x114f3db, 0x2f642a39, 0xff3807ab]
-    yield from run_fpunit(dut, stimulus_a, stimulus_b, add, get_rs_case)
+    yield from run_fpunit(dut, stimulus_a, stimulus_b, add, get_case)
     count += len(stimulus_a)
     print (count, "vectors passed")
 
-    yield from run_corner_cases(dut, count, add, get_rs_case)
-    yield from run_edge_cases(dut, count, add, get_rs_case, maxcount, num_loops)
+    yield from run_corner_cases(dut, count, add, get_case)
+    yield from run_edge_cases(dut, count, add, get_case, maxcount, num_loops)
 
 def test1(maxcount=10, num_loops=5):
-    dut = FPADD(width=32, id_wid=5, single_cycle=True)
+    dut = FPADD(width=32, single_cycle=False)
     run_simulation(dut, tbench(dut, maxcount, num_loops),
                         vcd_name="test_add.vcd")
 

diff --git a/src/ieee754/fpcommon/test/fpmux.py b/src/ieee754/fpcommon/test/fpmux.py
index 30e86a364dd6be48a230459b6f3a872323c9e3f7..19967e583bfbe6e9c215a96066e62a6dcdbcae52 100644 (file)
--- a/src/ieee754/fpcommon/test/fpmux.py
+++ b/src/ieee754/fpcommon/test/fpmux.py
@@ -141,6 +141,7 @@ class InputTestRandom(InputTest):
                     #op1 = 0x358637BD
                     #op1 = 0x3340f2a7
                     #op1 = 0x33D6BF95
+                    #op1 = 0x9885020648d8c0e8
                     vals.append((op1,))
                 else:
                     op1 = randint(0, (1<<width)-1)