start to get FP to INT working

diff --git a/src/ieee754/fcvt/pipeline.py b/src/ieee754/fcvt/pipeline.py
index 04855b1fcadc3d7c0af8d510276364ca76870837..05ad924150666efc3b090ff05f071f23f4d5276b 100644 (file)
--- a/src/ieee754/fcvt/pipeline.py
+++ b/src/ieee754/fcvt/pipeline.py
@@ -107,6 +107,10 @@ class FPCVTFloatToIntMod(Elaboratable):
         with m.If(a1.exp_n127):
             m.d.comb += self.o.z.eq(0)
 
+        # unsigned, -ve, return 0
+        with m.Elif((~signed) & a1.s):
+            m.d.comb += self.o.z.eq(0)
+
         # signed, exp too big
         with m.Elif(signed & (a1.e > Const(mz-1, espec))):
             with m.If(a1.s): # negative FP, so negative overrun
@@ -123,17 +127,18 @@ class FPCVTFloatToIntMod(Elaboratable):
 
         # ok exp should be in range: shift and round it
         with m.Else():
-            mantissa = Signal(mz, reset_less=True)
-            l = [0] * ms + [1] + [a1.m]
-            m.d.comb += mantissa.eq(Cat(*l))
+            mlen = max(a1.m_width, mz) + 5
+            mantissa = Signal(mlen, reset_less=True)
+            l = [0] * 2 + [a1.m[:-1]] + [1]
+            m.d.comb += mantissa[-a1.m_width-3:].eq(Cat(*l))
             m.d.comb += self.o.z.eq(mantissa)
 
             # shift
-            msr = FPEXPHigh(mz+3, espec[0])
+            msr = FPEXPHigh(mlen, espec[0])
             m.submodules.norm_exp = msr
-            m.d.comb += [msr.m_in[3:].eq(mantissa),
+            m.d.comb += [msr.m_in.eq(mantissa),
                          msr.e_in.eq(a1.e),
-                         msr.ediff.eq(Mux(signed, mz-1, mz))
+                         msr.ediff.eq(Mux(signed, mz-1, mz)-a1.e)
                         ]
 
             of = Overflow()

diff --git a/src/ieee754/fcvt/test/test_fcvt_f2int_pipe.py b/src/ieee754/fcvt/test/test_fcvt_f2int_pipe.py
index 592e5af0360abd260a2c8abc5ebe5ba5cf00e97f..ac962bebe243923454e5d80c0207885195eb682d 100644 (file)
--- a/src/ieee754/fcvt/test/test_fcvt_f2int_pipe.py
+++ b/src/ieee754/fcvt/test/test_fcvt_f2int_pipe.py
@@ -59,7 +59,7 @@ def test_int_pipe_i32_f32():
 def test_int_pipe_f16_ui16():
     # XXX softfloat-3 doesn't have ui16_to_xxx so use ui32 instead.
     # should be fine.
-    dut = FPCVTF2IntMuxInOut(16, 32, 4, op_wid=1)
+    dut = FPCVTF2IntMuxInOut(16, 16, 4, op_wid=1)
     runfp(dut, 16, "test_fcvt_f2int_pipe_f16_ui16", Float16, fcvt_f16_ui32,
                 True, n_vals=100)
 

diff --git a/src/ieee754/fpcommon/test/fpmux.py b/src/ieee754/fpcommon/test/fpmux.py
index cf638c96fb138d5af5022ec5a44678a57bd3d3ab..ef4fbdd08a7af394840e7ecdc1de5d3274cba62f 100644 (file)
--- a/src/ieee754/fpcommon/test/fpmux.py
+++ b/src/ieee754/fpcommon/test/fpmux.py
@@ -182,6 +182,10 @@ def create_random(num_rows, width, single_op=False, n_vals=10):
                 #op1 = 0x3001
                 #op1 = 0x3f2ad8eb
 
+                # f2int
+                #op1 = 0x4dc0
+                op1 = 0x3b81
+
                 vals.append((op1,))
             else:
                 op1 = randint(0, (1<<width)-1)