rename branch input data regs to spr1/2/3 according to FU Operand table

diff --git a/libreriscv b/libreriscv
index f6cbc0d518835dbfafc1d4cd3a3060aa2ddced53..18c7808cfdc2754cc9a21dd69d393b6c35f749ac 160000 (submodule)
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit f6cbc0d518835dbfafc1d4cd3a3060aa2ddced53
+Subproject commit 18c7808cfdc2754cc9a21dd69d393b6c35f749ac

diff --git a/src/soc/branch/main_stage.py b/src/soc/branch/main_stage.py
index b2cbc37a376411e265bbe0a65d91b73c1bd6ab97..09bb73df3fe1ede57337493417338a9f15989465 100644 (file)
--- a/src/soc/branch/main_stage.py
+++ b/src/soc/branch/main_stage.py
@@ -33,13 +33,12 @@ class BranchMainStage(PipeModBase):
         m = Module()
         comb = m.d.comb
         op = self.i.ctx.op
+        lk = op.lk # see PowerDecode2 as to why this is done
         nia_out, lr = self.o.nia_out, self.o.lr
 
         # obtain relevant instruction fields
         i_fields = self.fields.instrs['I']
-        lk = Signal(i_fields['LK'][0:-1].shape())
         aa = Signal(i_fields['AA'][0:-1].shape())
-        comb += lk.eq(i_fields['LK'][0:-1])
         comb += aa.eq(i_fields['AA'][0:-1])
 
         br_imm_addr = Signal(64, reset_less=True)
@@ -101,7 +100,7 @@ class BranchMainStage(PipeModBase):
                 comb += br_taken.eq(bc_taken)
             #### branch conditional reg ####
             with m.Case(InternalOp.OP_BCREG):
-                comb += br_imm_addr.eq(self.i.spr)
+                comb += br_imm_addr.eq(self.i.spr1) # SPR1 is set by decode unit
                 comb += br_taken.eq(bc_taken)
 
         ###### output next instruction address #####
@@ -109,11 +108,13 @@ class BranchMainStage(PipeModBase):
         comb += nia_out.data.eq(br_addr)
         comb += nia_out.ok.eq(br_taken)
 
-        ###### link register #####
+        ###### link register - only activate on operations marked as "lk" #####
 
         with m.If(lk):
+            # ctx.op.lk is the AND of the insn LK field *and* whether the
+            # op is to "listen" to the link field
             comb += lr.data.eq(self.i.cia + 4)
-        comb += lr.ok.eq(lk)
+            comb += lr.ok.eq(1)
 
         ###### and context #####
         comb += self.o.ctx.eq(self.i.ctx)

diff --git a/src/soc/branch/pipe_data.py b/src/soc/branch/pipe_data.py
index 606eb52d32e00eff74706738fa6a8d816ce1f2f3..3d3b9afbf026ea6b2ef40b1353082ad4a17f9352 100644 (file)
--- a/src/soc/branch/pipe_data.py
+++ b/src/soc/branch/pipe_data.py
@@ -49,22 +49,33 @@ class IntegerData:
 class BranchInputData(IntegerData):
     def __init__(self, pspec):
         super().__init__(pspec)
-        # For OP_BCREG, this will either be CTR, LR, or TAR
-        self.spr = Signal(64, reset_less=True)
-        self.ctr = Signal(64, reset_less=True)  # CTR
+        # Note: for OP_BCREG, SPR1 will either be CTR, LR, or TAR
+        # this involves the *decode* unit selecting the register, based
+        # on detecting the operand being bcctr, bclr or bctar
+
+        self.spr1 = Signal(64, reset_less=True) # see table above, SPR1
+        self.spr2 = Signal(64, reset_less=True) # see table above, SPR2
+        self.spr3 = Signal(64, reset_less=True) # see table above, SPR3
         self.cr = Signal(32, reset_less=True)   # Condition Register(s) CR0-7
         self.cia = Signal(64, reset_less=True)  # Current Instruction Address
 
+        # convenience variables.  not all of these are used at once
+        self.ctr = self.srr0 = self.hsrr0 = self.spr2
+        self.lr = self.tar = self.srr1 = self.hsrr1 = self.i.spr1
+        self.msr = self.spr3
+
     def __iter__(self):
         yield from super().__iter__()
-        yield self.ctr
-        yield self.spr
+        yield self.spr1
+        yield self.spr2
+        yield self.spr3
         yield self.cr
         yield self.cia
 
     def eq(self, i):
         lst = super().eq(i)
-        return lst + [self.ctr.eq(i.ctr), self.spr.eq(i.spr),
+        return lst + [self.spr1.eq(i.spr1), self.spr2.eq(i.spr2),
+                      self.spr3.eq(i.spr3),
                       self.cr.eq(i.cr), self.cia.eq(i.cia)]
 
 

diff --git a/src/soc/branch/test/test_pipe_caller.py b/src/soc/branch/test/test_pipe_caller.py
index d582e75694d63c7b2f73a3565326954a5141ef09..1553514bbfa9b0529d09e623c6bfd2e605c77b5c 100644 (file)
--- a/src/soc/branch/test/test_pipe_caller.py
+++ b/src/soc/branch/test/test_pipe_caller.py
@@ -159,7 +159,7 @@ class TestRunner(FHDLTestCase):
                     yield instruction.eq(ins)          # raw binary instr.
                     yield branch.p.data_i.cia.eq(simulator.pc.CIA.value)
                     yield branch.p.data_i.cr.eq(simulator.cr.get_range().value)
-                    yield branch.p.data_i.ctr.eq(simulator.spr['CTR'].value)
+                    yield branch.p.data_i.spr2.eq(simulator.spr['CTR'].value)
                     print(f"cr0: {simulator.crl[0].get_range()}")
                     yield Settle()
                     fn_unit = yield pdecode2.e.fn_unit