rename stb to "valid"

diff --git a/src/add/example_buf_pipe.py b/src/add/example_buf_pipe.py
index 37f866c36d1b463eba75c07f2bd7506d0a4acf1d..aab10a917e4c53b59439c122d5dde9950fbc1488 100644 (file)
--- a/src/add/example_buf_pipe.py
+++ b/src/add/example_buf_pipe.py
@@ -12,11 +12,11 @@
     where data will flow on *every* clock when the conditions are right.
 
     input acceptance conditions are when:
-        * incoming previous-stage strobe (i.p_stb) is HIGH
+        * incoming previous-stage strobe (i.p_valid) is HIGH
         * outgoing previous-stage busy   (o.p_busy) is LOW
 
     output transmission conditions are when:
-        * outgoing next-stage strobe (o.n_stb) is HIGH
+        * outgoing next-stage strobe (o.n_valid) is HIGH
         * outgoing next-stage busy   (i.n_busy) is LOW
 
     the tricky bit is when the input has valid data and the output is not
@@ -103,21 +103,21 @@ class ExampleStage:
 class IOAckIn:
 
     def __init__(self):
-        self.p_stb = Signal()  # >>in - comes in from PREVIOUS stage
+        self.p_valid = Signal()  # >>in - comes in from PREVIOUS stage
         self.n_busy = Signal() # in<< - comes in from the NEXT stage
 
 
 class IOAckOut:
 
     def __init__(self):
-        self.n_stb = Signal()  # out>> - goes out to the NEXT stage
+        self.n_valid = Signal()  # out>> - goes out to the NEXT stage
         self.p_busy = Signal() # <<out - goes out to the PREVIOUS stage
 
 
 class BufferedPipeline:
     """ buffered pipeline stage
 
-        stage-1   i.p_stb  >>in   stage   o.n_stb  out>>   stage+1
+        stage-1   i.p_valid  >>in   stage   o.n_valid  out>>   stage+1
         stage-1   o.p_busy <<out  stage   i.n_busy <<in    stage+1
         stage-1   i_data   >>in   stage   o_data   out>>   stage+1
                               |             |
@@ -128,12 +128,12 @@ class BufferedPipeline:
     def __init__(self):
         # input: strobe comes in from previous stage, busy comes in from next
         self.i = IOAckIn()
-        #self.i.p_stb = Signal()    # >>in - comes in from PREVIOUS stage
+        #self.i.p_valid = Signal()    # >>in - comes in from PREVIOUS stage
         #self.i.n_busy = Signal()   # in<< - comes in from the NEXT stage
 
         # output: strobe goes out to next stage, busy comes in from previous
         self.o = IOAckOut()
-        #self.o.n_stb = Signal()    # out>> - goes out to the NEXT stage
+        #self.o.n_valid = Signal()    # out>> - goes out to the NEXT stage
         #self.o.p_busy = Signal()   # <<out - goes out to the PREVIOUS stage
 
     def elaborate(self, platform):
@@ -141,34 +141,34 @@ class BufferedPipeline:
 
         # establish some combinatorial temporaries
         o_p_busyn = Signal(reset_less=True)
-        o_n_stbn = Signal(reset_less=True)
+        o_n_validn = Signal(reset_less=True)
         i_n_busyn = Signal(reset_less=True)
-        i_p_stb_o_p_busyn = Signal(reset_less=True)
+        i_p_valid_o_p_busyn = Signal(reset_less=True)
         m.d.comb += [i_n_busyn.eq(~self.i.n_busy),
-                     o_n_stbn.eq(~self.o.n_stb),
+                     o_n_validn.eq(~self.o.n_valid),
                      o_p_busyn.eq(~self.o.p_busy),
-                     i_p_stb_o_p_busyn.eq(self.i.p_stb & o_p_busyn),
+                     i_p_valid_o_p_busyn.eq(self.i.p_valid & o_p_busyn),
         ]
 
         # store result of processing in combinatorial temporary
-        with m.If(self.i.p_stb): # input is valid: process it
+        with m.If(self.i.p_valid): # input is valid: process it
             m.d.comb += self.stage.process()
         # if not in stall condition, update the temporary register
         with m.If(o_p_busyn): # not stalled
             m.d.sync += self.stage.update_buffer()
 
         #with m.If(self.i.p_rst): # reset
-        #    m.d.sync += self.o.n_stb.eq(0)
+        #    m.d.sync += self.o.n_valid.eq(0)
         #    m.d.sync += self.o.p_busy.eq(0)
         with m.If(i_n_busyn): # next stage is not busy
             with m.If(o_p_busyn): # not stalled
                 # nothing in buffer: send (processed) input direct to output
-                m.d.sync += [self.o.n_stb.eq(self.i.p_stb),
+                m.d.sync += [self.o.n_valid.eq(self.i.p_valid),
                              self.stage.update_output(),
                             ]
             with m.Else(): # o.p_busy is true, and something is in our buffer.
                 # Flush the [already processed] buffer to the output port.
-                m.d.sync += [self.o.n_stb.eq(1),
+                m.d.sync += [self.o.n_valid.eq(1),
                              self.stage.flush_buffer(),
                              # clear stall condition, declare register empty.
                              self.o.p_busy.eq(0),
@@ -176,22 +176,22 @@ class BufferedPipeline:
                 # ignore input, since o.p_busy is also true.
 
         # (i.n_busy) is true here: next stage is busy
-        with m.Elif(o_n_stbn): # next stage being told "not busy"
-            m.d.sync += [self.o.n_stb.eq(self.i.p_stb),
+        with m.Elif(o_n_validn): # next stage being told "not busy"
+            m.d.sync += [self.o.n_valid.eq(self.i.p_valid),
                          self.o.p_busy.eq(0), # Keep the buffer empty
                          # set the output data (from comb result)
                          self.stage.update_output(),
                         ]
-        # (i.n_busy) and (o.n_stb) both true:
-        with m.Elif(i_p_stb_o_p_busyn):
+        # (i.n_busy) and (o.n_valid) both true:
+        with m.Elif(i_p_valid_o_p_busyn):
             # If next stage *is* busy, and not stalled yet, accept input
-            m.d.sync += self.o.p_busy.eq(self.i.p_stb & self.o.n_stb)
+            m.d.sync += self.o.p_busy.eq(self.i.p_valid & self.o.n_valid)
 
         return m
 
     def ports(self):
-        return [self.i.p_stb, self.i.n_busy,
-                self.o.n_stb, self.o.p_busy,
+        return [self.i.p_valid, self.i.n_busy,
+                self.o.n_valid, self.o.p_busy,
                ]
 
 

diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
index baa344a91faa442b4b93d87d878f9db687ca3152..7f972454a2273abc3a44e480aa1b34c92f7f00b2 100644 (file)
--- a/src/add/test_buf_pipe.py
+++ b/src/add/test_buf_pipe.py
@@ -4,13 +4,13 @@ from example_buf_pipe import BufPipe
 from random import randint
 
 
-def check_o_n_stb(dut, val):
-    o_n_stb = yield dut.o.n_stb
-    assert o_n_stb == val
+def check_o_n_valid(dut, val):
+    o_n_valid = yield dut.o.n_valid
+    assert o_n_valid == val
 
-def check_o_n_stb2(dut, val):
-    o_n_stb = yield dut.o_n_stb
-    assert o_n_stb == val
+def check_o_n_valid2(dut, val):
+    o_n_valid = yield dut.o_n_valid
+    assert o_n_valid == val
 
 
 def testbench(dut):
@@ -22,30 +22,30 @@ def testbench(dut):
     #yield dut.i_p_rst.eq(0)
     yield dut.i.n_busy.eq(0)
     yield dut.stage.i_data.eq(5)
-    yield dut.i.p_stb.eq(1)
+    yield dut.i.p_valid.eq(1)
     yield
 
     yield dut.stage.i_data.eq(7)
-    yield from check_o_n_stb(dut, 0) # effects of i_p_stb delayed
+    yield from check_o_n_valid(dut, 0) # effects of i_p_valid delayed
     yield
-    yield from check_o_n_stb(dut, 1) # ok *now* i_p_stb effect is felt
+    yield from check_o_n_valid(dut, 1) # ok *now* i_p_valid effect is felt
 
     yield dut.stage.i_data.eq(2)
     yield
     yield dut.i.n_busy.eq(1) # begin going into "stall" (next stage says busy)
     yield dut.stage.i_data.eq(9)
     yield
-    yield dut.i.p_stb.eq(0)
+    yield dut.i.p_valid.eq(0)
     yield dut.stage.i_data.eq(12)
     yield
     yield dut.stage.i_data.eq(32)
     yield dut.i.n_busy.eq(0)
     yield
-    yield from check_o_n_stb(dut, 1) # buffer still needs to output
+    yield from check_o_n_valid(dut, 1) # buffer still needs to output
     yield
-    yield from check_o_n_stb(dut, 1) # buffer still needs to output
+    yield from check_o_n_valid(dut, 1) # buffer still needs to output
     yield
-    yield from check_o_n_stb(dut, 0) # buffer outputted, *now* we're done.
+    yield from check_o_n_valid(dut, 0) # buffer outputted, *now* we're done.
     yield
 
 
@@ -58,33 +58,33 @@ def testbench2(dut):
     #yield dut.i.p_rst.eq(0)
     yield dut.i_n_busy.eq(0)
     yield dut.i_data.eq(5)
-    yield dut.i_p_stb.eq(1)
+    yield dut.i_p_valid.eq(1)
     yield
 
     yield dut.i_data.eq(7)
-    yield from check_o_n_stb2(dut, 0) # effects of i_p_stb delayed 2 clocks
+    yield from check_o_n_valid2(dut, 0) # effects of i_p_valid delayed 2 clocks
     yield
-    yield from check_o_n_stb2(dut, 0) # effects of i_p_stb delayed 2 clocks
+    yield from check_o_n_valid2(dut, 0) # effects of i_p_valid delayed 2 clocks
 
     yield dut.i_data.eq(2)
     yield
-    yield from check_o_n_stb2(dut, 1) # ok *now* i_p_stb effect is felt
+    yield from check_o_n_valid2(dut, 1) # ok *now* i_p_valid effect is felt
     yield dut.i_n_busy.eq(1) # begin going into "stall" (next stage says busy)
     yield dut.i_data.eq(9)
     yield
-    yield dut.i_p_stb.eq(0)
+    yield dut.i_p_valid.eq(0)
     yield dut.i_data.eq(12)
     yield
     yield dut.i_data.eq(32)
     yield dut.i_n_busy.eq(0)
     yield
-    yield from check_o_n_stb2(dut, 1) # buffer still needs to output
+    yield from check_o_n_valid2(dut, 1) # buffer still needs to output
     yield
-    yield from check_o_n_stb2(dut, 1) # buffer still needs to output
+    yield from check_o_n_valid2(dut, 1) # buffer still needs to output
     yield
-    yield from check_o_n_stb2(dut, 1) # buffer still needs to output
+    yield from check_o_n_valid2(dut, 1) # buffer still needs to output
     yield
-    yield from check_o_n_stb2(dut, 0) # buffer outputted, *now* we're done.
+    yield from check_o_n_valid2(dut, 0) # buffer outputted, *now* we're done.
     yield
     yield
     yield
@@ -113,11 +113,11 @@ class Test3:
                     yield
                     continue
                 if send and self.i != len(self.data):
-                    yield self.dut.i.p_stb.eq(1)
+                    yield self.dut.i.p_valid.eq(1)
                     yield self.dut.stage.i_data.eq(self.data[self.i])
                     self.i += 1
                 else:
-                    yield self.dut.i.p_stb.eq(0)
+                    yield self.dut.i.p_valid.eq(0)
                 yield
 
     def rcv(self):
@@ -127,9 +127,9 @@ class Test3:
                 stall = randint(0, stall_range) == 0
                 yield self.dut.i.n_busy.eq(stall)
                 yield
-                o_n_stb = yield self.dut.o.n_stb
+                o_n_valid = yield self.dut.o.n_valid
                 i_n_busy = yield self.dut.i.n_busy
-                if not o_n_stb or i_n_busy:
+                if not o_n_valid or i_n_busy:
                     continue
                 o_data = yield self.dut.stage.o_data
                 assert o_data == self.data[self.o] + 1, \
@@ -154,15 +154,15 @@ def testbench4(dut):
         o_p_busy = yield dut.o_p_busy
         if not o_p_busy:
             if send and i != len(data):
-                yield dut.i_p_stb.eq(1)
+                yield dut.i_p_valid.eq(1)
                 yield dut.i_data.eq(data[i])
                 i += 1
             else:
-                yield dut.i_p_stb.eq(0)
+                yield dut.i_p_valid.eq(0)
         yield
-        o_n_stb = yield dut.o_n_stb
+        o_n_valid = yield dut.o_n_valid
         i_n_busy = yield dut.i_n_busy
-        if o_n_stb and not i_n_busy:
+        if o_n_valid and not i_n_busy:
             o_data = yield dut.o_data
             assert o_data == data[o] + 2, "%d-%d data %x not match %x\n" \
                                         % (i, o, o_data, data[o])
@@ -175,7 +175,7 @@ class BufPipe2:
     """
         connect these:  ------|---------------|
                               v               v
-        i_p_stb  >>in  pipe1 o_n_stb  out>> i_p_stb  >>in  pipe2
+        i_p_valid  >>in  pipe1 o_n_valid  out>> i_p_valid  >>in  pipe2
         o_p_busy <<out pipe1 i_n_busy <<in  o_p_busy <<out pipe2
         stage.i_data   >>in  pipe1 o_data   out>> stage.i_data   >>in  pipe2
     """
@@ -184,12 +184,12 @@ class BufPipe2:
         self.pipe2 = BufPipe()
 
         # input
-        self.i_p_stb = Signal()    # >>in - comes in from PREVIOUS stage
+        self.i_p_valid = Signal()    # >>in - comes in from PREVIOUS stage
         self.i_n_busy = Signal()   # in<< - comes in from the NEXT stage
         self.i_data = Signal(32) # >>in - comes in from the PREVIOUS stage
 
         # output
-        self.o_n_stb = Signal()    # out>> - goes out to the NEXT stage
+        self.o_n_valid = Signal()    # out>> - goes out to the NEXT stage
         self.o_p_busy = Signal()   # <<out - goes out to the PREVIOUS stage
         self.o_data = Signal(32) # out>> - goes out to the NEXT stage
 
@@ -198,18 +198,18 @@ class BufPipe2:
         m.submodules.pipe1 = self.pipe1
         m.submodules.pipe2 = self.pipe2
 
-        # connect inter-pipe input/output stb/busy/data
-        m.d.comb += self.pipe2.i.p_stb.eq(self.pipe1.o.n_stb)
+        # connect inter-pipe input/output valid/busy/data
+        m.d.comb += self.pipe2.i.p_valid.eq(self.pipe1.o.n_valid)
         m.d.comb += self.pipe1.i.n_busy.eq(self.pipe2.o.p_busy)
         m.d.comb += self.pipe2.stage.i_data.eq(self.pipe1.stage.o_data)
 
         # inputs/outputs to the module: pipe1 connections here (LHS)
-        m.d.comb += self.pipe1.i.p_stb.eq(self.i_p_stb)
+        m.d.comb += self.pipe1.i.p_valid.eq(self.i_p_valid)
         m.d.comb += self.o_p_busy.eq(self.pipe1.o.p_busy)
         m.d.comb += self.pipe1.stage.i_data.eq(self.i_data)
 
         # now pipe2 connections (RHS)
-        m.d.comb += self.o_n_stb.eq(self.pipe2.o.n_stb)
+        m.d.comb += self.o_n_valid.eq(self.pipe2.o.n_valid)
         m.d.comb += self.pipe2.i.n_busy.eq(self.i_n_busy)
         m.d.comb += self.o_data.eq(self.pipe2.stage.o_data)