remove extraneous clock cycle

diff --git a/src/test_bsv/tests/test_pinmux.py b/src/test_bsv/tests/test_pinmux.py
index 8cf5065c12b79364892ee6196b4a96c96bae1136..52b0add4aabc9ffa0e94bb79498b118eef958958 100644 (file)
--- a/src/test_bsv/tests/test_pinmux.py
+++ b/src/test_bsv/tests/test_pinmux.py
@@ -100,8 +100,6 @@ def pinmux_uart(dut):
     dut.EN_mux_lines_cell1_mux = 0
     dut.EN_mux_lines_cell2_mux = 0
 
-    yield Timer(2)
-
     # UART
     yield Timer(2)
     dut.peripheral_side_uart_tx_in = 1