add slave and master for rgbttl

diff --git a/src/bsv/bsv_lib/soc_template.bsv b/src/bsv/bsv_lib/soc_template.bsv
index addc7ce02838c2673afe5f40a92e771aa6050395..0e48a0e0a15f091f54a7ca54127bad2179494941 100644 (file)
--- a/src/bsv/bsv_lib/soc_template.bsv
+++ b/src/bsv/bsv_lib/soc_template.bsv
@@ -31,8 +31,11 @@ package Soc;
        import slow_peripherals::*;
        `include "defines.bsv"
        `include "instance_defines.bsv"
-    /*====== AXI4 Lite slave declarations =======*/
+    /*====== AXI4 slave declarations =======*/
 {3}
+    /*====== AXI4 Master declarations =======*/
+{4}
+
 
                `ifdef DMA
                        import DMA                               :: *;

diff --git a/src/bsv/peripheral_gen/base.py b/src/bsv/peripheral_gen/base.py
index 6c455fa8faeb1a798d6ecedde0bd3b44dd3d825f..ef8f881cc42b08c5db3b3e086489a3fce83def1b 100644 (file)
--- a/src/bsv/peripheral_gen/base.py
+++ b/src/bsv/peripheral_gen/base.py
@@ -9,6 +9,9 @@ class PBase(object):
         sname = self.get_iname(count)
         return "        interface PeripheralSide%s %s;" % (name.upper(), sname)
 
+    def has_axi_master(self):
+        return False
+
     def slowifdeclmux(self, name, count):
         return ''
 
@@ -45,14 +48,18 @@ class PBase(object):
                 "    `define %(bend)s  'h%(end)08X // %(comment)s" % locals(),
                 offs)
 
-    def axi_master_name(self, name, ifacenum):
+    def axi_master_name(self, name, ifacenum, typ=''):
         name = name.upper()
-        return "{0}{1}_laster_num".format(name, ifacenum)
+        return "{0}{1}_master_num".format(name, ifacenum)
 
     def axi_slave_name(self, name, ifacenum, typ=''):
         name = name.upper()
         return "{0}{1}_{2}slave_num".format(name, ifacenum, typ)
 
+    def axi_master_idx(self, idx, name, ifacenum, typ):
+        name = self.axi_master_name(name, ifacenum, typ)
+        return ("typedef {0} {1};".format(idx, name), 1)
+
     def axi_slave_idx(self, idx, name, ifacenum, typ):
         name = self.axi_slave_name(name, ifacenum, typ)
         return ("typedef {0} {1};".format(idx, name), 1)
@@ -203,6 +210,14 @@ mkplic_rule = """\
      endrule
 """
 
+axi_master_declarations= """\
+typedef 0 Dmem_master_num;
+typedef 1 Imem_master_num;
+{0}
+typedef TAdd#(LastGen_master_num, `ifdef Debug 1 `else 0 `endif ) Debug_master_num;
+typedef TAdd#(Debug_master_num, `ifdef DMA 1 `else 0 `endif ) DMA_master_num;
+typedef TAdd#(DMA_master_num,1) Num_Masters;
+"""
 
 axi_fastslave_declarations = """\
 {0}
@@ -281,6 +296,11 @@ class PeripheralIface(object):
             return ('', 0)
         return self.slow.axi_reg_def(start, self.ifacename, count)
 
+    def axi_master_idx(self, start, count, typ):
+        if not self.slow or not self.slow.has_axi_master():
+            return ('', 0)
+        return self.slow.axi_master_idx(start, self.ifacename, count, typ)
+
     def axi_slave_idx(self, start, count, typ):
         if not self.slow:
             return ('', 0)
@@ -358,7 +378,11 @@ class PeripheralInterfaces(object):
             for i in range(count):
                 if self.is_on_fastbus(name, i):
                     continue
-                (rdef, offs) = self.data[name].axi_slave_idx(start, i, idxtype)
+                if typ == 'master':
+                    fn = self.data[name].axi_master_idx
+                else:
+                    fn = self.data[name].axi_slave_idx
+                (rdef, offs) = fn(start, i, idxtype)
                 #print ("ifc", name, rdef, offs)
                 ret.append(rdef)
                 start += offs
@@ -374,6 +398,14 @@ class PeripheralInterfaces(object):
         return self._axi_num_idx(0, axi_fastslave_declarations, 'fastslave',
                                  'fast', *args)
 
+    def axi_master_idx(self, *args):
+        return self._axi_num_idx(2, axi_master_declarations, 'master',
+                                 'master', *args)
+
+    def axi_fastslave_idx(self, *args):
+        return self._axi_num_idx(0, axi_fastslave_declarations, 'fastslave',
+                                 'fast', *args)
+
     def axi_addr_map(self, *args):
         ret = []
         for (name, count) in self.ifacecount:

diff --git a/src/bsv/peripheral_gen/rgbttl.py b/src/bsv/peripheral_gen/rgbttl.py
index 1671d6517842f614e6fe1e9f60904170600ad0f0..9ac4b382fb835e8634a4be22dc676c771e381f8a 100644 (file)
--- a/src/bsv/peripheral_gen/rgbttl.py
+++ b/src/bsv/peripheral_gen/rgbttl.py
@@ -6,15 +6,9 @@ class rgbttl(PBase):
     def slowimport(self):
         return "    import rgbttl_dummy              :: *;"
 
-    def must_be_axi_master(self):
+    def has_axi_master(self):
         return True
 
-    def axi_slave_name(self, name, ifacenum):
-        return ''
-
-    def axi_slave_idx(self, idx, name, ifacenum, typ):
-        return ('', 0)
-
     def num_axi_regs32(self):
         return 10
 

diff --git a/src/bsv/pinmux_generator.py b/src/bsv/pinmux_generator.py
index 7844dfa1c976adcf9efaf8f246ea6c15856dacc2..85a81a51ef6e79ef5e20b24b4af7da91e724d805 100644 (file)
--- a/src/bsv/pinmux_generator.py
+++ b/src/bsv/pinmux_generator.py
@@ -135,6 +135,7 @@ def write_soc(soc, soct, p, ifaces, iocells):
     ifdecl = "" #ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
     regdef = ifaces.axi_reg_def()
     slavedecl = ifaces.axi_fastslave_idx()
+    mastdecl = ifaces.axi_master_idx()
     fnaddrmap = ifaces.axi_addr_map()
     mkfast = ifaces.mkfast_peripheral()
     mkcon = ifaces.mk_connection()
@@ -147,7 +148,7 @@ def write_soc(soc, soct, p, ifaces, iocells):
     ifacedef = ifaces.mk_ext_ifacedef()
     with open(soc, "w") as bsv_file:
         bsv_file.write(soct.format(imports, ifdecl, mkfast,
-                            slavedecl,
+                            slavedecl, mastdecl,
                             #'', '' #regdef, slavedecl,
                             #'', mkslow, #fnaddrmap, mkslow, mkcon, mkcellcon,
                             #pincon, inst, mkplic,