first test of down-converted load/store from 64 to 32 bit

diff --git a/src/soc/bus/wb_downconvert.py b/src/soc/bus/wb_downconvert.py
index 1e4389c2d344d10625005fcfd858ce4a69c2820a..2fe2a921c4631a54ee67b06e3fab276ecbe36e92 100644 (file)
--- a/src/soc/bus/wb_downconvert.py
+++ b/src/soc/bus/wb_downconvert.py
@@ -36,6 +36,8 @@ class WishboneDownConvert(Elaboratable):
         dw_to = len(slave.dat_w)
         ratio = dw_from//dw_to
 
+        print ("wb downconvert from to ratio", dw_from, dw_to, ratio)
+
         # # #
 
         read = Signal()

diff --git a/src/soc/config/test/test_loadstore.py b/src/soc/config/test/test_loadstore.py
index aab4d969b473bd86372f3dd991585370432e5203..9b8884a423ebb0cab5eee1fdc0d73157bee6e498 100644 (file)
--- a/src/soc/config/test/test_loadstore.py
+++ b/src/soc/config/test/test_loadstore.py
@@ -82,7 +82,8 @@ def tst_lsmemtype(ifacetype):
     pspec = TestMemPspec(ldst_ifacetype=ifacetype,
                          imem_ifacetype='', addr_wid=64,
                          mask_wid=4,
-                         reg_wid=32)
+                         wb_data_wid=32,
+                         reg_wid=64)
     dut = ConfigLoadStoreUnit(pspec).lsi
     vl = rtlil.convert(dut, ports=[])  # TODOdut.ports())
     with open("test_loadstore_%s.il" % ifacetype, "w") as f:

diff --git a/src/soc/minerva/units/loadstore.py b/src/soc/minerva/units/loadstore.py
index de3246e90515548354e5de8b388c4b62b73bb0be..3526709de5e179f334376d51f15230e125c50d8b 100644 (file)
--- a/src/soc/minerva/units/loadstore.py
+++ b/src/soc/minerva/units/loadstore.py
@@ -19,7 +19,7 @@ class LoadStoreUnitInterface:
         print(self.dbus.sel.shape())
         if isinstance(pspec.wb_data_wid, int):
             pspecslave = deepcopy(pspec)
-            pspecslave.data_wid = pspec.wb_data_wid
+            pspecslave.reg_wid = pspec.wb_data_wid
             self.slavebus = Record(make_wb_layout(pspecslave))
             self.cvt = WishboneDownConvert(self.dbus, self.slavebus)
         self.mask_wid = mask_wid = pspec.mask_wid
@@ -88,7 +88,7 @@ class BareLoadStoreUnit(LoadStoreUnitInterface, Elaboratable):
         m = Module()
 
         if hasattr(self, "cvt"):
-            m.submodules.cvt = cvt
+            m.submodules.cvt = self.cvt
 
         with m.If(self.dbus.cyc):
             with m.If(self.dbus.ack | self.dbus.err | ~self.m_valid_i):