yield port1.addr.ok.eq(1) # set ok
yield Settle()
yield from wait_addr(port1) # wait until addr ok
+ yield from wait_addr(port1) # wait until addr ok
+ exc_happened = yield port1.exc_o.happened
+ if exc_happened:
+ print("print fast exception happened")
+ yield port1.is_st_i.eq(0) # end
+ yield port1.addr.ok.eq(0) # set !ok
+ yield port1.is_dcbz_i.eq(0) # reset dcbz too
+ return "fast"
+
# yield # not needed, just for checking
# yield # not needed, just for checking
# assert "ST" for one cycle (required by the API)
yield port1.st.ok.eq(0)
yield from wait_busy(port1,debug="pi_st_E") # wait while busy
+ # TODO: fast exception handling
+
# can go straight to reset.
yield port1.is_st_i.eq(0) # end
yield port1.addr.ok.eq(0) # set !ok
yield port1.is_dcbz_i.eq(0) # reset dcbz too
+
+ return None
# copy of pi_st removed
data = 0xbeef
data2 = 0xf00f
#data = 0x4
- yield from pi_st(dut, addr1, data, 2, msr_pr)
- yield from pi_st(dut, addr2, data2, 2, msr_pr)
- result = yield from pi_ld(dut, addr1, 2, msr_pr)
- result2 = yield from pi_ld(dut, addr2, 2, msr_pr)
+ assert(yield from pi_st(dut, addr1, data, 2, msr_pr) is None)
+ assert(yield from pi_st(dut, addr2, data2, 2, msr_pr) is None)
+ result, exc = yield from pi_ld(dut, addr1, 2, msr_pr)
+ result2, exc2 = yield from pi_ld(dut, addr2, 2, msr_pr)
+ assert(exc is None)
+ assert(exc2 is None)
arg.assertEqual(data, result, "data %x != %x" % (result, data))
arg.assertEqual(data2, result2, "data2 %x != %x" % (result2, data2))
# now load both in a 32-bit load to make sure they're really consecutive
data3 = data | (data2 << 16)
- result3 = yield from pi_ld(dut, addr1, 4, msr_pr)
+ result3, exc3 = yield from pi_ld(dut, addr1, 4, msr_pr)
+ assert(exc3 is None)
arg.assertEqual(data3, result3, "data3 %x != %x" % (result3, data3))