'''
# ============================================================
pinmux = ''' '''
-digits = maketrans('0123456789', ' '*10) # delete space later
+digits = maketrans('0123456789', ' '*10) # delete space later
+
def cn(idx):
return "cell%s_mux" % str(idx)
+
for cell in muxed_cells:
pinmux = pinmux + " %s_out=" % cn(cell[0])
i = 0
while(i < len(cell) - 1):
pinmux = pinmux + "wr%s" % cn(cell[0]) + \
- "==" + str(i) + "?" + cell[i + 1] + "_io:\n\t\t\t"
+ "==" + str(i) + "?" + cell[i + 1] + "_io:\n\t\t\t"
if(i + 2 == len(cell) - 1):
pinmux = pinmux + cell[i + 2] + "_io"
i = i + 2
x = dictionary.get(temp)
if(x is None):
print(
- "ERROR: The signal : " +
- str(cell[i + 1]) +
- " of pinmap.txt isn't present in the current dictionary.\
+ "ERROR: The signal : " +
+ str(cell[i + 1]) +
+ " of pinmap.txt isn't present in the current dictionary.\
\nUpdate dictionary or fix-typo.")
exit(1)
if(x == "input"):
pinmux = pinmux + \
- mux_wire.format(cell[0], i, "wr" + cell[i + 1]) + "\n"
+ mux_wire.format(cell[0], i, "wr" + cell[i + 1]) + "\n"
elif(x == "inout"):
pinmux = pinmux + \
mux_wire.format(cell[0], i, "wr" + cell[i + 1] +
from UserDict import UserDict
+
class Pin(object):
""" pin interface declaration.
* name is the name of the pin
res += "<-mkDWire(0);"
return res
+
class Interface(object):
""" create an interface from a list of pinspecs.
each pinspec is a dictionary, see Pin class arguments
def wirefmtpin(self, pin):
return pin.wirefmt(self.ifacefmtoutfn, self.ifacefmtinfn,
- self.ifacefmtdecfn2)
+ self.ifacefmtdecfn2)
def ifacefmtdecpin(self, pin):
return pin.ifacefmt(self.ifacefmtdecfn)
count = int(l[1])
spec = self.read_spec(name)
self.ifaceadd(name, count, Interface(name, spec))
-
+
def ifaceadd(self, name, count, iface):
self.ifacecount.append((name, count))
self[name] = iface
# ========= Interface declarations ================ #
-mux_interface = Interface('cell', [{'name': 'mux', 'ready':False,
- 'enabled':False,
+mux_interface = Interface('cell', [{'name': 'mux', 'ready': False,
+ 'enabled': False,
'bitspec': '{1}', 'action': True}])
io_interface = IOInterface('io',
- [{'name': 'outputval', 'enabled': False},
- {'name': 'output_en', 'enabled': False},
- {'name': 'input_en', 'enabled': False},
- {'name': 'pullup_en', 'enabled': False},
- {'name': 'pulldown_en', 'enabled': False},
- {'name': 'drivestrength', 'enabled': False},
- {'name': 'pushpull_en', 'enabled': False},
- {'name': 'opendrain_en', 'enabled': False},
- {'name': 'inputval', 'action': True, 'io': True},
- ])
+ [{'name': 'outputval', 'enabled': False},
+ {'name': 'output_en', 'enabled': False},
+ {'name': 'input_en', 'enabled': False},
+ {'name': 'pullup_en', 'enabled': False},
+ {'name': 'pulldown_en', 'enabled': False},
+ {'name': 'drivestrength', 'enabled': False},
+ {'name': 'pushpull_en', 'enabled': False},
+ {'name': 'opendrain_en', 'enabled': False},
+ {'name': 'inputval', 'action': True, 'io': True},
+ ])
# == Peripheral Interface definitions == #
# these are the interface of the peripherals to the pin mux
if __name__ == '__main__':
uartinterface_decl = Interface('uart',
- [{'name': 'rx'},
- {'name': 'tx', 'action': True},
- ])
+ [{'name': 'rx'},
+ {'name': 'tx', 'action': True},
+ ])
twiinterface_decl = Interface('twi',
- [{'name': 'sda', 'outen': True},
- {'name': 'scl', 'outen': True},
- ])
+ [{'name': 'sda', 'outen': True},
+ {'name': 'scl', 'outen': True},
+ ])
def _pinmunge(p, sep, repl, dedupe=True):
""" munges the text so it's easier to compare.
for cell in muxed_cells:
bsv_file.write(mux_interface.ifacefmt(cell[0],
- int(math.log(len(cell) - 1, 2))))
+ int(math.log(len(cell) - 1, 2))))
bsv_file.write('''
endinterface
// values for each mux assigned to a CELL
''')
for cell in muxed_cells:
- bsv_file.write(muxwire.format(cell[0], int(math.log(len(cell) - 1, 2))))
-
+ bsv_file.write(muxwire.format(
+ cell[0], int(math.log(len(cell) - 1, 2))))
bsv_file.write(
'''\n // following wires capture the values sent to the IO Cell''')
''')
for cell in muxed_cells:
bsv_file.write(mux_interface.ifacedef(cell[0],
- int(math.log(len(cell) - 1, 2))))
+ int(math.log(len(cell) - 1, 2))))
bsv_file.write('''
endinterface;
interface peripheral_side = interface PeripheralSide
with open('bsv_src/bus.bsv', 'w') as bsv_file:
bsv_file.write(axi4_lite.format(ADDR_WIDTH, DATA_WIDTH))
# ##################################################
-