add jtag IO to experiment10

diff --git a/experiments10/add.py b/experiments10/add.py
index 9b45f1caca9fdf167d0af484141803216b0c1930..19a900443d4d5c9087d154f8599e5dc2b4a42d25 100644 (file)
--- a/experiments10/add.py
+++ b/experiments10/add.py
@@ -20,6 +20,10 @@ class ADD(Elaboratable):
 
         # set up JTAG
         self.jtag = TAP(ir_width=4)
+        self.jtag.bus.tck.name = 'tck'
+        self.jtag.bus.tms.name = 'tms'
+        self.jtag.bus.tdo.name = 'tdo'
+        self.jtag.bus.tdi.name = 'tdi'
 
         # have to create at least one shift register
         self.sr = self.jtag.add_shiftreg(ircode=4, length=3)
@@ -28,7 +32,7 @@ class ADD(Elaboratable):
         m = Module()
 
         m.submodules.jtag = jtag = self.jtag
-        m.d.comb += self.sr.i.eq(self.sr.o) # loopback test
+        #m.d.comb += self.sr.i.eq(self.sr.o) # loopback test
 
         # do a simple "add"
         m.d.sync += self.f.eq(self.a + self.b)
@@ -43,4 +47,8 @@ def create_ilang(dut, ports, test_name):
 
 if __name__ == "__main__":
     alu = ADD(width=4)
-    create_ilang(alu, [alu.a, alu.b, alu.f], "add")
+    create_ilang(alu, [alu.a, alu.b, alu.f,
+                       alu.jtag.bus.tck,
+                        alu.jtag.bus.tms,
+                        alu.jtag.bus.tdo,
+                        alu.jtag.bus.tdi], "add")

diff --git a/experiments10/coriolis2/ioring.py b/experiments10/coriolis2/ioring.py
index 5b43d14fee0ec5fd3a1234a74c030637f0691295..3842e0ed8c0e480a2e9e91ccfe773e9ef52adbef 100644 (file)
--- a/experiments10/coriolis2/ioring.py
+++ b/experiments10/coriolis2/ioring.py
@@ -22,15 +22,22 @@ chip = { 'pads.ioPadGauge' : 'pxlib',
         [ 'p_f1'    , 'f(1)',   'f(1)' ], # , 'f_oe' ],
         [ 'p_f2'    , 'f(2)',   'f(2)' ], # , 'f_oe' ],
         [ 'p_f3'    , 'f(3)',   'f(3)' ], # , 'f_oe' ],
+        # JTAG
+        [ 'p_tck_0'    , 'tck',   'tck'], # 2nd clock
+        [ 'p_tms_0'    , 'tms',   'tms'],
+        [ 'p_tdo_0'    , 'tdo',   'tdo'],
+        [ 'p_tdi_0'    , 'tdi',   'tdi'],
         ],
         'pads.south'      :
-            [ 'p_a1', 'p_vddick_0', 'p_vssick_0' , 'p_a0'       ],
+            [ 'p_a1', 'p_vddick_0', 'p_vssick_0' , 'p_a0', 'p_a2', 'p_b3', ],
        'pads.east'       :
-            [ 'p_a2', 'p_a3'       , 'p_b3'        , 'p_b2'       ],
+            [ 'p_tck_0', # 2nd clock
+                'p_tms_0', 'p_tdo_0', 'p_tdi_0',
+                'p_b2'       ],
        'pads.north'      :
-            [ 'p_b1', 'p_vddeck_0', 'p_b0'        , 'p_vsseck_0', 'rst' ],
+            [ 'p_b1', 'p_vddeck_0', 'p_b0', 'p_vsseck_0', 'rst' ],
        'pads.west'       :
-            [ 'p_f3', 'p_f2'       , 'p_clk_0', 'p_f1'       , 'p_f0' ],
+            [ 'p_f3', 'p_f2'       , 'p_clk_0', 'p_f1' , 'p_f0', 'p_a3' ],
        'core.size'       : ( l( 1200), l( 1200) ),
        'chip.size'       : ( l(3200), l(3200) ),
        'pads.useCoreSize'  : True,

diff --git a/experiments10/coriolis2/settings.py b/experiments10/coriolis2/settings.py
index 85b6b479c4bffdb476af61653ad33460b4b97267..f93e33d99202736654357e8bca453cc61e7bb1bd 100644 (file)
--- a/experiments10/coriolis2/settings.py
+++ b/experiments10/coriolis2/settings.py
@@ -48,7 +48,7 @@ env = af.getEnvironment()
 env.addSYSTEM_LIBRARY( library=cellsTop+'/nsxlib', mode=CRL.Environment.Prepend )
 env.addSYSTEM_LIBRARY( library=cellsTop+'/mpxlib', mode=CRL.Environment.Prepend )
 #env.setCLOCK( '^clk$|m_clock' )
-env.setCLOCK( 'clk|ck|cki' )
+env.setCLOCK( 'clk' )
 env.setPOWER( 'vdd' )
 env.setGROUND( 'vss' )