projects / ls2.git / commitdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: d5d8c74)
Revert "Put sysclk2x back under system reset control"
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 10 Apr 2022 17:15:15 +0000 (18:15 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 10 Apr 2022 17:15:15 +0000 (18:15 +0100)
This reverts commit 793d05f2ef2e38891a4fb2ffbd6c77631fb86873.

src/ecp5_crg.py patch | blob | history

diff --git a/src/ecp5_crg.py b/src/ecp5_crg.py
index d588376c4ee7388f797042ef94924ca3d74ba474..86358d48e91d26dcfc6eb4d9e821b99063cce242 100644 (file)
--- a/src/ecp5_crg.py
+++ b/src/ecp5_crg.py
@@ -219,7 +219,7 @@ class ECP5CRG(Elaboratable):
         m.submodules.pll = pll = PLL(ClockSignal("rawclk"), reset=~pod_done|~reset)
 
         # Generating sync2x (200Mhz) and init (25Mhz) from extclk
-        cd_sync2x = ClockDomain("sync2x", local=False)
+        cd_sync2x = ClockDomain("sync2x", local=False, reset_less=True)
         cd_sync2x_unbuf = ClockDomain("sync2x_unbuf",
                                       local=False, reset_less=True)
         cd_init = ClockDomain("init", local=False)