whitespace cleanup, 80 char limit

diff --git a/src/ls2.py b/src/ls2.py
index f9f61cc3d5e94505435aafe1741bbe0fa3583680..6652b60bf553b7fdb60ae504e2e851e056160e94 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -672,13 +672,19 @@ def build_platform(fpga, firmware):
     ethmac_0_pins = None
     if platform is not None and fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim']:
             ethmac_0_pins = platform.request("ethmac_0", 0,
-                                        dir={"mtx_clk":"i", "mtxd":"o", "mtxen":"o",
-                                             "mtxerr":"o", "mrx_clk":"i", "mrxd":"i",
-                                             "mrxdv":"i", "mrxerr":"i", "mcoll":"i",
+                                        dir={"mtx_clk":"i", "mtxd":"o",
+                                             "mtxen":"o",
+                                             "mtxerr":"o", "mrx_clk":"i", 
+                                             "mrxd":"i",
+                                             "mrxdv":"i", "mrxerr":"i", 
+                                             "mcoll":"i",
                                              "mcrs":"i", "mdc":"o", "md":"io"},
-                                        xdr={"mtx_clk": 0, "mtxd": 0, "mtxen": 0,
-                                             "mtxerr": 0, "mrx_clk": 0, "mrxd": 0,
-                                             "mrxdv": 0, "mrxerr": 0, "mcoll": 0,
+                                        xdr={"mtx_clk": 0, "mtxd": 0, 
+                                             "mtxen": 0,
+                                             "mtxerr": 0, "mrx_clk": 0, 
+                                             "mrxd": 0,
+                                             "mrxdv": 0, "mrxerr": 0, 
+                                             "mcoll": 0,
                                              "mcrs": 0, "mdc": 0, "md": 0})
 
     # Get HyperRAM pins