set power type in fake pll vdd/vss

diff --git a/experiments10_verilog/pll.py b/experiments10_verilog/pll.py
index 03a6cccb2cc409ea891ffc8c1226988aa645ba0b..07a89a981b7e4cbf4cc42e90c22a825e53c34e40 100644 (file)
--- a/experiments10_verilog/pll.py
+++ b/experiments10_verilog/pll.py
@@ -237,6 +237,8 @@ def _load():
         nets['div_out_test'].setDirection( Net.Direction.OUT )
         nets['vco_test_ana'].setDirection( Net.Direction.OUT )
         nets['out_v'].setDirection( Net.Direction.OUT )
+        nets['vdd'].setType( Net.Type.POWER )
+        nets['vss'].setType( Net.Type.GROUND )
 
         # create series of stepped pins
         x = space*20

diff --git a/experiments9/pll.py b/experiments9/pll.py
index 03a6cccb2cc409ea891ffc8c1226988aa645ba0b..07a89a981b7e4cbf4cc42e90c22a825e53c34e40 100644 (file)
--- a/experiments9/pll.py
+++ b/experiments9/pll.py
@@ -237,6 +237,8 @@ def _load():
         nets['div_out_test'].setDirection( Net.Direction.OUT )
         nets['vco_test_ana'].setDirection( Net.Direction.OUT )
         nets['out_v'].setDirection( Net.Direction.OUT )
+        nets['vdd'].setType( Net.Type.POWER )
+        nets['vss'].setType( Net.Type.GROUND )
 
         # create series of stepped pins
         x = space*20