move cell_bit_width function

diff --git a/src/bsv/actual_pinmux.py b/src/bsv/actual_pinmux.py
index 890aefe7a5bb98676bc27b17a9cb5c7e05f7e2cc..78b9ba36aa5b1ca955b547dc28d545d4f41c75db 100644 (file)
--- a/src/bsv/actual_pinmux.py
+++ b/src/bsv/actual_pinmux.py
@@ -1,3 +1,4 @@
+import math
 from string import digits
 try:
     from string import maketrans
@@ -23,6 +24,13 @@ dedicated_wire = '''
 digits = maketrans('0123456789', ' ' * 10)  # delete space later
 
 
+def get_cell_bit_width(p):
+    max_num_cells = 0
+    for cell in p.muxed_cells:
+        max_num_cells = max(len(cell) - 1, max_num_cells)
+    return int(math.log(max_num_cells+1, 2))
+
+
 def cn(idx):  # idx is an integer
     return "cell%s_mux" % str(idx)
 
@@ -65,6 +73,7 @@ def init(p, ifaces):
 
         last line doesn't need selector-logic, obviously.
     """
+    p.cell_bitwidth = get_cell_bit_width(p)
     p.pinmux = ' '
     global dedicated_wire
     fmtstr = "\t\t\twr%s == %d ? %s :%s\n" # mux-selector format

diff --git a/src/bsv/pinmux_generator.py b/src/bsv/pinmux_generator.py
index 6b4ae07aed69a56ad0b096c5148a2c87f9b265c9..68b1896de74880e983f159bc19fbfb39a62ccee1 100644 (file)
--- a/src/bsv/pinmux_generator.py
+++ b/src/bsv/pinmux_generator.py
@@ -20,7 +20,6 @@ import shutil
 import os
 import os.path
 import time
-import math
 
 # project module imports
 from bsv.interface_decl import Interfaces, mux_interface, io_interface
@@ -109,20 +108,13 @@ def write_bus(bus, p, ifaces):
         ifaces.busfmt(bsv_file)
 
 
-def get_cell_bit_width(p):
-    max_num_cells = 0
-    for cell in p.muxed_cells:
-        max_num_cells = max(len(cell) - 1, max_num_cells)
-    return int(math.log(max_num_cells+1, 2))
-
-
 def write_pmp(pmp, p, ifaces):
     # package and interface declaration followed by
     # the generic io_cell definition
     with open(pmp, "w") as bsv_file:
         bsv_file.write(header)
 
-        cell_bit_width = 'Bit#(%d)' % get_cell_bit_width(p)
+        cell_bit_width = 'Bit#(%d)' % p.cell_bitwidth
         bsv_file.write('''\
    interface MuxSelectionLines;
 
@@ -219,7 +211,7 @@ package PinTop;
         // declare the registers which will be used to mux the IOs
 '''.format(p.ADDR_WIDTH, p.DATA_WIDTH))
 
-        cell_bit_width = str(get_cell_bit_width(p))
+        cell_bit_width = str(p.cell_bitwidth)
         for cell in p.muxed_cells:
             bsv_file.write('''
                 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(