unnecessary signal rename ivalid_i to ii_valid (reverting)

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 2e5fa5bdc26922bd90a415bc42691276573b0df1..65643115173926ed7a7499c0c75ad60e45116275 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -117,7 +117,7 @@ class NonProductionCore(Elaboratable):
             self.sv_pred_dm = Signal() # TODO: SIMD width
 
         # issue/valid/busy signalling
-        self.ii_valid = Signal(reset_less=True) # instruction is valid
+        self.ivalid_i = Signal(reset_less=True) # instruction is valid
         self.issue_i = Signal(reset_less=True)
         self.busy_o = Signal(name="corebusy_o", reset_less=True)
 
@@ -226,7 +226,7 @@ class NonProductionCore(Elaboratable):
             sync += counter.eq(counter - 1)
             comb += self.busy_o.eq(1)
 
-        with m.If(self.ii_valid): # run only when valid
+        with m.If(self.ivalid_i): # run only when valid
             with m.Switch(self.e.do.insn_type):
                 # check for ATTN: halt if true
                 with m.Case(MicrOp.OP_ATTN):

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 5c40b3c9612abf37fe86058a8ef2adf6e39fd027..dad804d4e2fbd7471821805690d999c54f9726a9 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -860,7 +860,7 @@ class TestIssuerInternal(Elaboratable):
 
         # temporaries
         core_busy_o = core.busy_o                 # core is busy
-        core_ii_valid = core.ii_valid             # instruction is valid
+        core_ivalid_i = core.ivalid_i             # instruction is valid
         core_issue_i = core.issue_i               # instruction is issued
         insn_type = core.e.do.insn_type           # instruction MicroOp type
 
@@ -870,7 +870,7 @@ class TestIssuerInternal(Elaboratable):
             with m.State("INSN_START"):
                 comb += exec_insn_o_ready.eq(1)
                 with m.If(exec_insn_i_valid):
-                    comb += core_ii_valid.eq(1)  # instruction is valid
+                    comb += core_ivalid_i.eq(1)  # instruction is valid
                     comb += core_issue_i.eq(1)  # and issued
                     sync += sv_changed.eq(0)
                     sync += pc_changed.eq(0)
@@ -879,7 +879,7 @@ class TestIssuerInternal(Elaboratable):
             # instruction started: must wait till it finishes
             with m.State("INSN_ACTIVE"):
                 with m.If(insn_type != MicrOp.OP_NOP):
-                    comb += core_ii_valid.eq(1) # instruction is valid
+                    comb += core_ivalid_i.eq(1) # instruction is valid
                 # note changes to PC and SVSTATE
                 with m.If(self.state_nia.wen & (1<<StateRegs.SVSTATE)):
                     sync += sv_changed.eq(1)

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index b137e2b5c0072918673b904b82e9e2c15a212979..a35545024e23ba05a8ad71ac96e2500e0c5b4612 100644 (file)
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -240,7 +240,7 @@ class TestRunner(FHDLTestCase):
         m = Module()
         comb = m.d.comb
         instruction = Signal(32)
-        ii_valid = Signal()
+        ivalid_i = Signal()
 
         pspec = TestMemPspec(ldst_ifacetype='testpi',
                              imem_ifacetype='',
@@ -253,7 +253,7 @@ class TestRunner(FHDLTestCase):
         l0 = core.l0
 
         comb += core.raw_opcode_i.eq(instruction)
-        comb += core.ii_valid.eq(ii_valid)
+        comb += core.ivalid_i.eq(ivalid_i)
 
         # temporary hack: says "go" immediately for both address gen and ST
         ldst = core.fus.fus['ldst0']
@@ -291,7 +291,7 @@ class TestRunner(FHDLTestCase):
                     # ask the decoder to decode this binary data (endian'd)
                     yield core.bigendian_i.eq(bigendian)  # little / big?
                     yield instruction.eq(ins)          # raw binary instr.
-                    yield ii_valid.eq(1)
+                    yield ivalid_i.eq(1)
                     yield Settle()
                     # fn_unit = yield pdecode2.e.fn_unit
                     #fuval = self.funit.value
@@ -302,7 +302,7 @@ class TestRunner(FHDLTestCase):
                     yield Settle()
 
                     yield from wait_for_busy_clear(core)
-                    yield ii_valid.eq(0)
+                    yield ivalid_i.eq(0)
                     yield
 
                     print("sim", code)