create a JTAG platform and connect it up. jtagremote is actually running

diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py
index 87521ebd0519f110de29ca2a48320261459ba048..c797a43d8ba56d698e624ac7a0dc152f31226fe6 100755 (executable)
--- a/src/soc/litex/florent/sim.py
+++ b/src/soc/litex/florent/sim.py
@@ -164,6 +164,23 @@ class LibreSoCSim(SoCSDRAM):
             self.add_constant("MEMTEST_DATA_DEBUG", 1)
 
 
+        # add JTAG platform pins
+        platform.add_extension([
+            ("jtag", 0,
+                Subsignal("tck",  Pins(1)),
+                Subsignal("tms", Pins(1)),
+                Subsignal("tdi", Pins(1)),
+                Subsignal("tdo", Pins(1)),
+            )
+        ])
+
+        jtagpads = platform.request("jtag")
+        self.comb += self.cpu.jtag_tck.eq(jtagpads.tck)
+        self.comb += self.cpu.jtag_tms.eq(jtagpads.tms)
+        self.comb += self.cpu.jtag_tdi.eq(jtagpads.tdi)
+        self.comb += jtagpads.tdo.eq(self.cpu.jtag_tdo)
+
+
         # Debug ---------------------------------------------------------------
         if not debug:
             return