fix write-after-write hazard checking

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 0f29a7f5a334c0b9245edf05b1b8cf41554db0f1..debff9da1d6b37ea55dcb018bc9476b5fe25a25f 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -752,7 +752,7 @@ class NonProductionCore(ControlBase):
             wvset = wv.s # write-vec bit-level hazard ctrl
             wvclr = wv.r # write-vec bit-level hazard ctrl
             wvchk = wv.q # write-after-write hazard check
-            wvchk_qint = wv.q_int # write-after-write hazard check, delayed
+            wvchk_qint = wv.q # write-after-write hazard check, NOT delayed
 
         fspecs = fspec
         if not isinstance(fspecs, list):