PLL sys group has 2 select lines and PLL Lock out

diff --git a/src/spec/pinfunctions.py b/src/spec/pinfunctions.py
index e3c97f3efa9bcacf8a990ad68888ab56d695cc01..a20d93f4a5dca552e5a5791fc0bfcf4531d7619f 100644 (file)
--- a/src/spec/pinfunctions.py
+++ b/src/spec/pinfunctions.py
@@ -286,7 +286,7 @@ def vdd(suffix, bank):
 
 def sys(suffix, bank):
     return (['CLK-', 'RST-', 'PLLCLK-', 'PLLOUT+',
-             'CSEL0-', 'CSEL1-', 'CSEL2-'], [], 'CLK')
+             'CSEL0-', 'CSEL1-', 'PLLOCK+'], [], 'CLK')
 
 # list functions by name here