disconnect pll clock, connected in peripheral interconnect

diff --git a/pinmux b/pinmux
index 87d20b3d00b9b1d8be84fb4f1ddfabcc1b6d93b8..c676c0197579cd8211a3db3582c82855e14b4ff0 160000 (submodule)
--- a/pinmux
+++ b/pinmux
@@ -1 +1 @@
-Subproject commit 87d20b3d00b9b1d8be84fb4f1ddfabcc1b6d93b8
+Subproject commit c676c0197579cd8211a3db3582c82855e14b4ff0

diff --git a/src/soc/litex/florent b/src/soc/litex/florent
index d7e76c5ba83b12e8466f16294ad052b62f679ce1..6f31d65eb4433b66d64fcf924f2c0eb3cb4b9b3b 160000 (submodule)
--- a/src/soc/litex/florent
+++ b/src/soc/litex/florent
@@ -1 +1 @@
-Subproject commit d7e76c5ba83b12e8466f16294ad052b62f679ce1
+Subproject commit 6f31d65eb4433b66d64fcf924f2c0eb3cb4b9b3b

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 7def3ad3e1069f514faedba31f52ff1aacabf54e..8bf44ae62f35a935a9ccf667d93b7c370a943468 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -1253,7 +1253,7 @@ class TestIssuer(Elaboratable):
             self.pll_test_o = Signal(reset_less=True)
             self.pll_vco_o = Signal(reset_less=True)
             self.clk_sel_i = Signal(2, reset_less=True)
-            self.ref_clk = Signal(reset_less=True)
+            self.ref_clk =  ClockSignal() # can't rename it but that's ok
             self.pllclk_clk = ClockSignal("pllclk")
 
     def elaborate(self, platform):
@@ -1278,8 +1278,7 @@ class TestIssuer(Elaboratable):
             comb += pllclk.eq(pll.clk_pll_o)
 
             # wire up external 24mhz to PLL
-            comb += pll.clk_24_i.eq(ClockSignal())
-
+            #comb += pll.clk_24_i.eq(self.ref_clk)
             # output 18 mhz PLL test signal, and analog oscillator out
             comb += self.pll_test_o.eq(pll.pll_test_o)
             comb += self.pll_vco_o.eq(pll.pll_vco_o)
@@ -1324,6 +1323,7 @@ class TestIssuer(Elaboratable):
         ports.append(ResetSignal())
         if self.pll_en:
             ports.append(self.clk_sel_i)
+            ports.append(self.pll.clk_24_i)
             ports.append(self.pll_test_o)
             ports.append(self.pll_vco_o)
             ports.append(self.pllclk_clk)

diff --git a/src/soc/soc-cocotb-sim b/src/soc/soc-cocotb-sim
index 9f0665b83a6b12fe784efc9d4398ebd0af1fd2bc..25e5b98b796402abc482241775bfe727c9d0a22e 160000 (submodule)
--- a/src/soc/soc-cocotb-sim
+++ b/src/soc/soc-cocotb-sim
@@ -1 +1 @@
-Subproject commit 9f0665b83a6b12fe784efc9d4398ebd0af1fd2bc
+Subproject commit 25e5b98b796402abc482241775bfe727c9d0a22e