Cleanup

diff --git a/src/ieee754/cordic/pipe_data.py b/src/ieee754/cordic/pipe_data.py
index a284bff1755adb45df7aad5fc728658d46fc9165..a477d20014d0494420f784b9600a62ca1bc46797 100644 (file)
--- a/src/ieee754/cordic/pipe_data.py
+++ b/src/ieee754/cordic/pipe_data.py
@@ -1,7 +1,8 @@
 from nmigen import Signal, Const
-from nmutil.dynamicpipe import DynamicPipe, SimpleHandshakeRedir
+from nmutil.dynamicpipe import SimpleHandshakeRedir
 import math
 
+
 class CordicInitialData:
 
     def __init__(self, pspec):
@@ -14,6 +15,7 @@ class CordicInitialData:
     def eq(self, i):
         return [self.z0.eq(i.z0)]
 
+
 class CordicData:
 
     def __init__(self, pspec):

diff --git a/src/ieee754/cordic/sin_cos.py b/src/ieee754/cordic/sin_cos.py
index cbcef5ae3ef4f11c5a6d8630f51f2e282b76d843..fcfef762551c301390ce743d720bf5597fec0f2d 100644 (file)
--- a/src/ieee754/cordic/sin_cos.py
+++ b/src/ieee754/cordic/sin_cos.py
@@ -2,7 +2,7 @@
 # later be used to verify the operation of a pipelined version
 
 # see http://bugs.libre-riscv.org/show_bug.cgi?id=208
-from nmigen import Module, Elaboratable, Signal, Memory, signed
+from nmigen import Module, Elaboratable, Signal, Memory
 from nmigen.cli import rtlil
 import math
 from enum import Enum, unique
@@ -63,7 +63,6 @@ class CORDIC(Elaboratable):
         comb = m.d.comb
         sync = m.d.sync
 
-
         # Calculate initial amplitude?
         An = 1.0
         for i in range(self.iterations):
@@ -118,9 +117,9 @@ class CORDIC(Elaboratable):
         return [self.cos, self.sin, self.z0,
                 self.ready, self.start]
 
+
 if __name__ == '__main__':
     dut = CORDIC(8)
     vl = rtlil.convert(dut, ports=dut.ports())
     with open("cordic.il", "w") as f:
         f.write(vl)
-

diff --git a/src/ieee754/cordic/sin_cos_pipe_stage.py b/src/ieee754/cordic/sin_cos_pipe_stage.py
index 1a1a4ec943a3272e2fbc27f2c97ae09f0c2d7e4d..79ad65904ace4c38441a735f8f9dc51e34302fc5 100644 (file)
--- a/src/ieee754/cordic/sin_cos_pipe_stage.py
+++ b/src/ieee754/cordic/sin_cos_pipe_stage.py
@@ -1,8 +1,9 @@
-from nmigen import Module, Signal, Cat, Mux
+from nmigen import Module, Signal
 from nmutil.pipemodbase import PipeModBase
 from ieee754.cordic.pipe_data import CordicData, CordicInitialData
 import math
 
+
 class CordicInitialStage(PipeModBase):
     def __init__(self, pspec):
         super().__init__(pspec, "cordicinit")
@@ -28,7 +29,6 @@ class CordicInitialStage(PipeModBase):
         return m
 
 
-
 class CordicStage(PipeModBase):
     def __init__(self, pspec, stagenum):
         super().__init__(pspec, "cordicstage%d" % stagenum)

diff --git a/src/ieee754/cordic/sin_cos_pipeline.py b/src/ieee754/cordic/sin_cos_pipeline.py
index 58d84e385a5eef7d10701f2e63871932dff4e261..42dd6fc5df114c9d080d6491c795322b9663181b 100644 (file)
--- a/src/ieee754/cordic/sin_cos_pipeline.py
+++ b/src/ieee754/cordic/sin_cos_pipeline.py
@@ -1,11 +1,9 @@
 from nmutil.singlepipe import ControlBase
-from nmutil.concurrentunit import ReservationStations, num_bits
 from nmutil.pipemodbase import PipeModBaseChain
 
 from ieee754.cordic.sin_cos_pipe_stage import (
     CordicStage, CordicInitialStage)
-from ieee754.cordic.pipe_data import (CordicPipeSpec, CordicData,
-                                      CordicInitialData)
+
 
 class CordicPipeChain(PipeModBaseChain):
     def __init__(self, pspec, stages):
@@ -14,7 +12,7 @@ class CordicPipeChain(PipeModBaseChain):
 
     def get_chain(self):
         return self.stages
-        
+
 
 class CordicBasePipe(ControlBase):
     def __init__(self, pspec):
@@ -29,7 +27,7 @@ class CordicBasePipe(ControlBase):
             self.cordicstages.append(stage)
 
         self._eqs = self.connect(self.cordicstages)
-        
+
     def elaborate(self, platform):
         m = ControlBase.elaborate(self, platform)
         for i, stage in enumerate(self.cordicstages):

diff --git a/src/ieee754/cordic/test/test_pipe.py b/src/ieee754/cordic/test/test_pipe.py
index bcfd563f0d936d3abaabf883474cb55a51b055e7..809ca7f7f5ae0f249c4e4679a681d9e4cb1d9a12 100644 (file)
--- a/src/ieee754/cordic/test/test_pipe.py
+++ b/src/ieee754/cordic/test/test_pipe.py
@@ -1,5 +1,5 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Passive
+from nmigen.back.pysim import Simulator, Passive
 from nmigen.test.utils import FHDLTestCase
 
 from ieee754.cordic.sin_cos_pipeline import CordicBasePipe
@@ -57,14 +57,12 @@ class SinCosTestCase(FHDLTestCase):
                     except StopIteration:
                         break
 
-
         sim.add_sync_process(writer_process)
         sim.add_sync_process(reader_process)
         with sim.write_vcd("pipeline.vcd", "pipeline.gtkw", traces=[
                 z, x, y]):
             sim.run()
 
-
     def test_rand(self):
         fracbits = 16
         M = (1 << fracbits)
@@ -79,6 +77,5 @@ class SinCosTestCase(FHDLTestCase):
         self.run_test(iter(inputs), iter(outputs), fracbits=fracbits)
 
 
-
 if __name__ == "__main__":
     unittest.main()