Simplify obtaining the PC from the register file

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index 98d428400a222bfd30533f1fb979ed31c7c41ab2..6f7c8ffdc87e3a983c724a06d4a8026131bda575 100644 (file)
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -173,7 +173,7 @@ def check_regs(dut, sim, core, test, code):
     dut.assertEqual(e_ca, ca, "ca mismatch %s" % (repr(code)))
 
     # Check the PC as well
-    state = core.regs.rf['state']
+    state = core.regs.state
     pc = yield state.r_ports['cia'].data_o
     e_pc = sim.pc.CIA.value
     dut.assertEqual(e_pc, pc)