comment out changing SPR 720 because 720 is not supported by the MMU pipe

diff --git a/src/soc/fu/mmu/test/test_issuer_mmu_rom.py b/src/soc/fu/mmu/test/test_issuer_mmu_rom.py
index 9f5e786df00214652fc7335a975c66741558fab0..2552b14b03bb5ac08c6a14f86bac3694f1220500 100644 (file)
--- a/src/soc/fu/mmu/test/test_issuer_mmu_rom.py
+++ b/src/soc/fu/mmu/test/test_issuer_mmu_rom.py
@@ -34,11 +34,13 @@ default_mem = { 0x10000:    # PARTITION_TABLE_2
 class MMUTestCase(TestAccumulatorBase):
     # MMU on microwatt handles MTSPR, MFSPR, DCBZ and TLBIE.
     # libre-soc has own SPR unit
+    # libre-soc MMU supports MTSPR and MFSPR but **ONLY** for the subset
+    # of SPRs it actually does.
     # other instructions here -> must be load/store
 
     def case_mmu_ldst(self):
         lst = [
-                "mtspr 720, 1",
+                #"mtspr 720, 1", # XXX do not execute unsupported instructions
                 "lhz 3, 0(1)"      # load some data
               ]