Fix pre-layout simulation with 4K SRAM blocks.

diff --git a/ls180/pre_pnr/Makefile b/ls180/pre_pnr/Makefile
index 4fbc60f119e0df5a3bff4b559bc82469c4c3962f..6a60bb45b0e76d11e73bc6d73a8cac17012c0d28 100644 (file)
--- a/ls180/pre_pnr/Makefile
+++ b/ls180/pre_pnr/Makefile
@@ -7,6 +7,7 @@ TOPLEVEL_LANG := verilog
 # within soc repo, as submodule, this works after "make ls180"
 # is run inside the litex/florent subdirectory
 VERILOG_SOURCES := \
+  ../SPBlock_512W64B8W.v \
   ../../../litex/florent/libresoc.v \
   ../../../litex/florent/ls180.v \
 # END VERILOG_SOURCES

diff --git a/ls180/pre_pnr/run_iverilog_ls180.sh b/ls180/pre_pnr/run_iverilog_ls180.sh
index 68bb2663e5b63daf74027b1dcbc55f27dcb8792a..1d5c42dd08517e1a6f590614c831a267cb56e10b 100755 (executable)
--- a/ls180/pre_pnr/run_iverilog_ls180.sh
+++ b/ls180/pre_pnr/run_iverilog_ls180.sh
@@ -1,10 +1,16 @@
 #!/bin/sh
 
+if grep -q ls180sram4k ../../../litex/florent/ls180.v; then
+  top=ls180sram4k
+else
+  top=ls180
+fi
+
 touch mem.init mem_1.init mem_2.init mem_3.init mem_4.init
 # Only run test in reset state as running CPU takes too much time to simulate
 make \
   SIM=icarus \
-  TOPLEVEL=ls180 \
+  TOPLEVEL=$top \
   COCOTB_RESULTS_FILE=results_iverilog_ls180.xml \
   COCOTB_HDL_TIMEUNIT=100ps \
   TESTCASE="idcode_reset,idcodesvf_reset,boundary_scan_reset,wishbone_basic" \