investigating why write-enable not getting passed through

on nmigen_soc sram

diff --git a/src/soc/bus/test/test_minerva.py b/src/soc/bus/test/test_minerva.py
index 299c93791b601011f78bcbbd091538cb379a3f0a..c813a77c24cbf8540e3e3b9daafa0dae992f4d65 100644 (file)
--- a/src/soc/bus/test/test_minerva.py
+++ b/src/soc/bus/test/test_minerva.py
@@ -10,19 +10,24 @@ class TestSRAMBareLoadStoreUnit(BareLoadStoreUnit):
     def elaborate(self, platform):
         m = super().elaborate(platform)
         comb = m.d.comb
-        # small 32-entry Memory
-        memory = Memory(width=self.addr_wid, depth=32)
+        # small 16-entry Memory
+        memory = Memory(width=self.data_wid, depth=16)
         m.submodules.sram = sram = SRAM(memory=memory, granularity=8,
                                         features={'cti', 'bte', 'err'})
         dbus = self.dbus
 
         # directly connect the wishbone bus of LoadStoreUnitInterface to SRAM
         # note: SRAM is a target (slave), dbus is initiator (master)
-        fanouts = ['adr', 'dat_w', 'sel', 'cyc', 'stb', 'we', 'cti', 'bte']
+        fanouts = ['dat_w', 'sel', 'cyc', 'stb', 'we', 'cti', 'bte']
         fanins = ['dat_r', 'ack', 'err']
         for fanout in fanouts:
+            print ("fanout", fanout, getattr(sram.bus, fanout).shape(),
+                                     getattr(dbus, fanout).shape())
+            comb += getattr(sram.bus, fanout).eq(getattr(dbus, fanout))
             comb += getattr(sram.bus, fanout).eq(getattr(dbus, fanout))
         for fanin in fanins:
             comb += getattr(dbus, fanin).eq(getattr(sram.bus, fanin))
+        # SRAM is row-addressed, so ignore LSBs
+        comb += sram.bus.adr.eq(dbus.adr[self.adr_lsbs:])
 
         return m

diff --git a/src/soc/config/test/test_loadstore.py b/src/soc/config/test/test_loadstore.py
index 783fe002493ce5b6cf5570b33712b397df12bbed..cdcba940f1bd5a0526ffc5bb0dfa6f64f11087de 100644 (file)
--- a/src/soc/config/test/test_loadstore.py
+++ b/src/soc/config/test/test_loadstore.py
@@ -14,6 +14,7 @@ def write_to_addr(dut, addr, value):
     yield dut.x_mask_i.eq(-1)
     yield dut.x_valid_i.eq(1)
     yield dut.x_stall_i.eq(1)
+    yield dut.m_valid_i.eq(1)
     yield
     yield
     
@@ -46,7 +47,9 @@ def write_byte(dut, addr, val):
     yield dut.x_st_i.eq(1)
     yield dut.x_st_data_i.eq(val << (offset * 8))
     yield dut.x_mask_i.eq(1 << offset)
+    print ("write_byte", addr, hex(1<<offset), hex(val<<(offset*8)))
     yield dut.x_valid_i.eq(1)
+    yield dut.m_valid_i.eq(1)
 
     yield
     yield dut.x_st_i.eq(0)
@@ -66,6 +69,7 @@ def read_byte(dut, addr):
         yield
     assert (yield dut.x_valid_i)
     val = (yield dut.m_ld_data_o)
+    print ("read_byte", addr, offset, hex(val))
     return (val >> (offset * 8)) & 0xff
 
 
@@ -73,7 +77,7 @@ def tst_lsmemtype(ifacetype):
     m = Module()
     Pspec = namedtuple('Pspec', ['ldst_ifacetype',
                                  'addr_wid', 'mask_wid', 'reg_wid'])
-    pspec = Pspec(ldst_ifacetype=ifacetype, addr_wid=64, mask_wid=4, reg_wid=64)
+    pspec = Pspec(ldst_ifacetype=ifacetype, addr_wid=64, mask_wid=4, reg_wid=32)
     dut = ConfigLoadStoreUnit(pspec).lsi
     m.submodules.dut = dut
 
@@ -87,14 +91,16 @@ def tst_lsmemtype(ifacetype):
         for addr, val in enumerate(values):
             yield from write_to_addr(dut, addr << 2, val)
             x = yield from read_from_addr(dut, addr << 2)
-            print ("addr, val", addr, val, x)
+            print ("addr, val", addr, hex(val), hex(x))
             assert x == val
 
         values = [random.randint(0, 255) for x in range(16*4)]
         for addr, val in enumerate(values):
             yield from write_byte(dut, addr, val)
-        for addr, val in enumerate(values):
+            x = yield from read_from_addr(dut, addr << 2)
+            print ("addr, val", addr, hex(val), hex(x))
             x = yield from read_byte(dut, addr)
+            print ("addr, val", addr, hex(val), hex(x))
             assert x == val
 
     sim.add_sync_process(process)
@@ -102,5 +108,5 @@ def tst_lsmemtype(ifacetype):
         sim.run()
 
 if __name__ == '__main__':
-    tst_lsmemtype('testmem')
     tst_lsmemtype('test_bare_wb')
+    tst_lsmemtype('testmem')