document partsig operators
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 10 Feb 2020 20:39:54 +0000 (20:39 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 10 Feb 2020 20:39:54 +0000 (20:39 +0000)
src/ieee754/part/partsig.py

index 157ea35f6deafca56b8b56b81e8898fc8e8b8c9d..5977bca64a04875930725220cba1cae046aca80b 100644 (file)
@@ -273,6 +273,7 @@ class PartitionedSignal:
             ``1`` if an odd number of bits are set, ``0`` if an
                   even number of bits are set.
         """
+        # XXXX TODO: return partition-mask-sized set of bits
         raise NotImplementedError
         return Operator("r^", [self])
 
@@ -285,4 +286,5 @@ class PartitionedSignal:
             ``0`` if ``premise`` is true and ``conclusion`` is not,
             ``1`` otherwise.
         """
+        # amazingly, this should actually work.
         return ~premise | conclusion