mmu.py add line I forgot to translate from mmu.vhdl

diff --git a/src/soc/experiment/mmu.py b/src/soc/experiment/mmu.py
index 8775652bb91d83d49f6afeb253dcb4d1b0750281..d5cba5a2ff4fd00ad4c4e94588a0f218545173f1 100644 (file)
--- a/src/soc/experiment/mmu.py
+++ b/src/soc/experiment/mmu.py
@@ -566,6 +566,7 @@ class AddrShifter(Elaboratable):
 #               pt_valid := r.pt3_valid;
             with m.Else():
                 comb += pgtbl.eq(r.pt3_valid)
+                comb += pt_valid.eq(r.pt3_valid)
 #           end if;
 
 #           -- rts == radix tree size, # address bits being translated