oops forgot to initialise base class of TestMemLoadStoreUnit

diff --git a/src/soc/experiment/lsmem.py b/src/soc/experiment/lsmem.py
index d829292051aeb5cbe69be01450ff9c0a37c97cb6..da9c73acfc3af8653bba5c747eda6f5821261cac 100644 (file)
--- a/src/soc/experiment/lsmem.py
+++ b/src/soc/experiment/lsmem.py
@@ -6,15 +6,10 @@ from nmigen.cli import rtlil
 
 
 class TestMemLoadStoreUnit(LoadStoreUnitInterface, Elaboratable):
-    def __init__(self, addr_wid=32, mask_wid=4, data_wid=32):
-        super().__init__()
-        self.regwid = data_wid
-        self.addrwid = addr_wid
-        self.mask_wid = mask_wid
 
     def elaborate(self, platform):
         m = Module()
-        regwid, addrwid, mask_wid = self.regwid, self.addrwid, self.mask_wid
+        regwid, addrwid, mask_wid = self.data_wid, self.addr_wid, self.mask_wid
         adr_lsb = self.adr_lsbs
 
         # limit TestMemory to 2^6 entries of regwid size

diff --git a/src/soc/experiment/pi2ls.py b/src/soc/experiment/pi2ls.py
index 8e6b2ccc6c0f605cf24980c74df78d3f55ab348d..32ed0a8a0ed4de7efb986d3500b5c21003a1c075 100644 (file)
--- a/src/soc/experiment/pi2ls.py
+++ b/src/soc/experiment/pi2ls.py
@@ -34,6 +34,7 @@ class Pi2LSUI(Elaboratable):
 
     def __init__(self, name, pi=None, lsui=None,
                              regwid=64, mask_wid=8, addrwid=48):
+        print ("pi2lsui reg mask addr", regwid, mask_wid, addrwid)
         self.addrbits = mask_wid
         if pi is None:
             pi = PortInterface(name="%s_pi", regwid=regwid, addrwid=addrwid)