Add 10/100 MAC pins for Versa boards and enable MAC

Tested to not interfere with main SoC in simulation,
not tested further at this point.

diff --git a/simsoc.ys b/simsoc.ys
index fcfb354682ff15825f81f48574289181be5470ce..77d3d6d9f388f4a5f867b5f79a493ff1e40fe8e0 100644 (file)
--- a/simsoc.ys
+++ b/simsoc.ys
@@ -18,6 +18,34 @@ read_verilog  ../uart16550/rtl/verilog/uart_tfifo.v
 read_verilog  ../uart16550/rtl/verilog/uart_wb.v
 read_verilog  ../tercel-qspi/tercel/phy.v 
 read_verilog  ../tercel-qspi/tercel/wishbone_spi_master.v
+read_verilog  ../ethmac/rtl/verilog
+read_verilog  ../ethmac/rtl/verilog/eth_clockgen.v
+read_verilog  ../ethmac/rtl/verilog/eth_cop.v
+read_verilog  ../ethmac/rtl/verilog/eth_crc.v
+read_verilog  ../ethmac/rtl/verilog/eth_fifo.v
+read_verilog  ../ethmac/rtl/verilog/eth_maccontrol.v
+read_verilog  ../ethmac/rtl/verilog/ethmac_defines.v
+read_verilog  ../ethmac/rtl/verilog/eth_macstatus.v
+read_verilog  ../ethmac/rtl/verilog/ethmac.v
+read_verilog  ../ethmac/rtl/verilog/eth_miim.v
+read_verilog  ../ethmac/rtl/verilog/eth_outputcontrol.v
+read_verilog  ../ethmac/rtl/verilog/eth_random.v
+read_verilog  ../ethmac/rtl/verilog/eth_receivecontrol.v
+read_verilog  ../ethmac/rtl/verilog/eth_registers.v
+read_verilog  ../ethmac/rtl/verilog/eth_register.v
+read_verilog  ../ethmac/rtl/verilog/eth_rxaddrcheck.v
+read_verilog  ../ethmac/rtl/verilog/eth_rxcounters.v
+read_verilog  ../ethmac/rtl/verilog/eth_rxethmac.v
+read_verilog  ../ethmac/rtl/verilog/eth_rxstatem.v
+read_verilog  ../ethmac/rtl/verilog/eth_shiftreg.v
+read_verilog  ../ethmac/rtl/verilog/eth_spram_256x32.v
+read_verilog  ../ethmac/rtl/verilog/eth_top.v
+read_verilog  ../ethmac/rtl/verilog/eth_transmitcontrol.v
+read_verilog  ../ethmac/rtl/verilog/eth_txcounters.v
+read_verilog  ../ethmac/rtl/verilog/eth_txethmac.v
+read_verilog  ../ethmac/rtl/verilog/eth_txstatem.v
+read_verilog  ../ethmac/rtl/verilog/eth_wishbone.v
+read_verilog  ../ethmac/rtl/verilog/timescale.v
 
 read_verilog  ./external_core_top.v
 

diff --git a/src/ls2.py b/src/ls2.py
index 5a8546465e3e2f9af9c926cc53dd278006b27e03..1956a8182d2c87bdcdcfccf0879bebcaf66d35e9 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -44,7 +44,7 @@ from gram.phy.fakephy import FakePHY, SDRAM_VERBOSE_STD, SDRAM_VERBOSE_DBG
 from gram.modules import MT41K256M16, MT41K64M16
 from gram.frontend.wishbone import gramWishbone
 
-# SPI
+# SPI / Ethernet MAC
 from nmigen.build import Resource
 from nmigen.build import Subsignal
 from nmigen.build import Pins
@@ -557,6 +557,9 @@ class DDR3SoC(SoC, Elaboratable):
             self.spi0.add_verilog_source(fname, platform)
 
         if hasattr(self, "eth0"):
+            # add ethernet submodule
+            m.submodules.eth0 = ethmac = self.eth0
+
             # add EthMAC verilog source. assumes a directory
             # structure where the opencores ethmac has been checked out
             # in a common subdirectory as:
@@ -694,16 +697,27 @@ def build_platform(fpga, firmware):
 
     # Get Ethernet RMII resource pins
     ethmac_0_pins = None
-    if False and platform is not None and \
+    if platform is not None and \
        fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim']:
-        # TODO, like this, which needs a patch to nmigen_boards
-        # from nmigen_boards.resources.interfaces import RMIIResource
-        # hyperram_ios = RMIIResource(0, cs_n="V12 V14 U12 U14",
-        #                                dq="D4 D3 F4 F3 G2 H2 D2 E2",
-        #                                rwds="U13", rst_n="T13", ck_p="V10",
-        #                                attrs=Attrs(IOSTANDARD="LVCMOS33"))
-        #platform.add_resources(hyperram_ios)
-        #hyperram_pins = platform.request("hyperram")
+        # Mainly on X3 connector, MDIO on X4 due to lack of pins
+        ethmac_0_ios = [
+            Resource("ethmac_0", 0,
+                     Subsignal("mtx_clk",   Pins("B19", dir="i")),
+                     Subsignal("mtxd",      Pins("B12 B9 E6 D6", dir="o")),
+                     Subsignal("mtxen",     Pins("E7", dir="o")),
+                     Subsignal("mtxerr",    Pins("D7", dir="o")),
+                     Subsignal("mrx_clk",   Pins("B11", dir="i")),
+                     Subsignal("mrxd",      Pins("B6 E9 D9 B8", dir="i")),
+                     Subsignal("mrxdv",     Pins("C8", dir="i")),
+                     Subsignal("mrxerr",    Pins("D8", dir="i")),
+                     Subsignal("mcoll",     Pins("E8", dir="i")),
+                     Subsignal("mcrs",      Pins("C7", dir="i")),
+                     Subsignal("mdc",       Pins("B18", dir="o")),
+                     Subsignal("md",        Pins("A18", dir="io")),
+                     Attrs(PULLMODE="NONE", DRIVE="8", SLEWRATE="FAST",
+                           IO_TYPE="LVCMOS33"))
+        ]
+        platform.add_resources(ethmac_0_ios)
         ethmac_0_pins = platform.request("ethmac_0", 0,
                                         dir={"mtx_clk":"i", "mtxd":"o",
                                              "mtxen":"o",
@@ -719,6 +733,7 @@ def build_platform(fpga, firmware):
                                              "mrxdv": 0, "mrxerr": 0, 
                                              "mcoll": 0,
                                              "mcrs": 0, "mdc": 0, "md": 0})
+    print ("ethmac pins", ethmac_0_pins)
 
     # Get HyperRAM pins
     hyperram_pins = None