Pinmux now accepts dummy pinset to change port names

diff --git a/src/spec/pinmux.py b/src/spec/pinmux.py
index 3c9b5c80823c8eb4f237d10027eeaef85f62f0ff..63c7f6f48926ac8fdaef68db581bc9a94dbc4403 100644 (file)
--- a/src/spec/pinmux.py
+++ b/src/spec/pinmux.py
@@ -23,9 +23,12 @@ else:
 from iomux import IOMuxBlockSingle, io_layout
 from simple_gpio import SimpleGPIO, GPIOManager, csrbus_layout
 
+dummy_pinspec = {"name": "A2", "mux0": "gpio0", "mux1": "UART3_TX",
+                 "mux2": "PWM0", "mux3": "sda0"}
+
 class PinMuxBlockSingle(Elaboratable):
 
-    def __init__(self, wb_wordsize):
+    def __init__(self, wb_wordsize, pinspec):
         print("1-bit Pin Mux Block with JTAG")
         self.n_banks = 4
         self.n_gpios = 1
@@ -37,21 +40,20 @@ class PinMuxBlockSingle(Elaboratable):
         spec.addr_wid = 30
         spec.mask_wid = 4
         spec.reg_wid = self.wb_wordsize*8
-        self.bus = Record(make_wb_layout(spec), name="pinmux_wb")
 
         temp = []
         for i in range(1, self.n_banks):
-            temp_str = "periph%d" % i
+            temp_str = "%s" % (pinspec["mux%d" % i])
             temp.append(Record(name=temp_str, layout=io_layout))
         self.periph_ports = Array(temp)
 
-        self.pad_port = Record(name="IOPad", layout=io_layout)
+        self.pad_port = Record(name=pinspec["name"], layout=io_layout)
 
         self.iomux = IOMuxBlockSingle(self.n_banks)
         self.gpio = SimpleGPIO(self.wb_wordsize, self.n_gpios)
         # This is probably easier to extend in future by bringing out WB
         # interface to top-level
-        #self.bus = self.gpio.bus
+        self.bus = self.gpio.bus
 
     def elaborate(self, platform):
         m = Module()
@@ -68,18 +70,18 @@ class PinMuxBlockSingle(Elaboratable):
 
         # Connect up modules and signals
         # WB bus connection
-        m.d.comb += [gpio.bus.adr.eq(bus.adr),
-                     gpio.bus.dat_w.eq(bus.dat_w),
-                     bus.dat_r.eq(gpio.bus.dat_r),
-                     gpio.bus.sel.eq(bus.sel),
-                     gpio.bus.cyc.eq(bus.cyc),
-                     gpio.bus.stb.eq(bus.stb),
-                     bus.ack.eq(gpio.bus.ack),
-                     gpio.bus.we.eq(bus.we),
-                     bus.err.eq(gpio.bus.err),
-                     gpio.bus.cti.eq(bus.cti), # Cycle Type Identifier
-                     gpio.bus.bte.eq(bus.bte) # Burst Type Extension
-                    ]
+        #m.d.comb += [gpio.bus.adr.eq(bus.adr),
+        #             gpio.bus.dat_w.eq(bus.dat_w),
+        #             bus.dat_r.eq(gpio.bus.dat_r),
+        #             gpio.bus.sel.eq(bus.sel),
+        #             gpio.bus.cyc.eq(bus.cyc),
+        #             gpio.bus.stb.eq(bus.stb),
+        #             bus.ack.eq(gpio.bus.ack),
+        #             gpio.bus.we.eq(bus.we),
+        #             bus.err.eq(gpio.bus.err),
+        #             gpio.bus.cti.eq(bus.cti), # Cycle Type Identifier
+        #             gpio.bus.bte.eq(bus.bte) # Burst Type Extension
+        #            ]
 
         m.d.comb += iomux.bank.eq(gpio.gpio_ports[0].bank)
 
@@ -104,7 +106,7 @@ class PinMuxBlockSingle(Elaboratable):
         """ Get member signals for Verilog form. """
         for field in self.pad_port.fields.values():
             yield field
-        for field in self.gpio.bus.fields.values():
+        for field in self.bus.fields.values():
             yield field
         for bank in range(len(self.periph_ports)):
             for field in self.periph_ports[bank].fields.values():
@@ -113,7 +115,7 @@ class PinMuxBlockSingle(Elaboratable):
     def ports(self):
         return list(self)
 
-def gen_gtkw_doc(module_name, wordsize, n_banks, filename):
+def gen_gtkw_doc(module_name, wordsize, n_banks, filename, pinspec):
     # GTKWave doc generation
     style = {
         '': {'base': 'hex'},
@@ -137,10 +139,10 @@ def gen_gtkw_doc(module_name, wordsize, n_banks, filename):
     traces.append(wb_traces)
 
     for bank in range(0, n_banks):
-        temp_traces = ('Bank%d' % bank, [
-                        ('bank%d__i' % bank, 'in'),
-                        ('bank%d__o' % bank, 'out'),
-                        ('bank%d__oe' % bank, 'out')
+        temp_traces = ('mux%d' % bank, [
+                        ('%s__i' % (pinspec["mux%d" % bank]), 'in'),
+                        ('%s__o' % (pinspec["mux%d" % bank]), 'in'),
+                        ('%s__oe' % (pinspec["mux%d" % bank]), 'in')
                       ])
         traces.append(temp_traces)
 
@@ -148,10 +150,10 @@ def gen_gtkw_doc(module_name, wordsize, n_banks, filename):
                     ('bank[%d:0]' % ((n_banks-1).bit_length()-1), 'in')
                   ])
     traces.append(temp_traces)
-    temp_traces = ('IO port to pad', [
-                    ('IO__i', 'in'),
-                    ('IO__o', 'out'),
-                    ('IO__oe', 'out')
+    temp_traces = ('IO port to pad named: %s' % pinspec["name"], [
+                    ('%s__i' % pinspec["name"], 'in'),
+                    ('%s__o' % pinspec["name"], 'in'),
+                    ('%s__oe' % pinspec["name"], 'in')
                   ])
     traces.append(temp_traces)
     #print(traces)
@@ -162,14 +164,15 @@ def gen_gtkw_doc(module_name, wordsize, n_banks, filename):
 def sim_iomux():
     filename = "test_gpio_pinmux" # Doesn't include extension
     wb_wordsize = 4
-    dut = PinMuxBlockSingle(wb_wordsize)
+
+    dut = PinMuxBlockSingle(wb_wordsize, dummy_pinspec)
     vl = rtlil.convert(dut, ports=dut.ports())
     with open(filename+".il", "w") as f:
         f.write(vl)
 
     print("Bus dir:")
-    print(dut.gpio.bus.adr)
-    print(dut.gpio.bus.fields)
+    print(dut.bus.adr)
+    print(dut.bus.fields)
 
     m = Module()
     m.submodules.pinmux = dut
@@ -182,7 +185,8 @@ def sim_iomux():
     with sim_writer:
         sim.run()
 
-    gen_gtkw_doc("top.pinmux", wb_wordsize, dut.n_banks, filename)
+    gen_gtkw_doc("top.pinmux", wb_wordsize, dut.n_banks, filename,
+                 dummy_pinspec)
 
 def test_gpio_pinmux(dut):
     print("------START----------------------")