add discussion links and bugreport

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 872ed5bb6591a3b3e4f02c36eb90ef7c4ad62d98..abef5d6d3fdc34270deaec349a4e3f90c4123c78 100644 (file)
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -13,6 +13,8 @@ Links:
 
 * https://libre-soc.org/3d_gpu/architecture/set_associative_cache.jpg
 * https://bugs.libre-soc.org/show_bug.cgi?id=469
+* https://libre-soc.org/irclog-microwatt/%23microwatt.2021-12-07.log.html
+  (discussion about brams for ECP5)
 
 """
 

diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index 845ed5ec39ab955d661f8646ea35f9d1cd8336eb..470f57180dd3171324d09b9621eee2a65a5f266f 100644 (file)
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -17,6 +17,13 @@ TODO (in no specific order):
   write TAG_BITS width which may not match full ram blocks and might
   cause muxes to be inferred for "partial writes".
 * Check if making the read size of PLRU a ROM helps utilization
+
+Links:
+
+* https://bugs.libre-soc.org/show_bug.cgi?id=485
+* https://libre-soc.org/irclog-microwatt/%23microwatt.2021-12-07.log.html
+  (discussion about brams for ECP5)
+
 """
 
 from enum import (Enum, unique)