attempting to get VERSA_ECP5 and Icarus Sim to work with ASync Bridge

diff --git a/src/ls2.py b/src/ls2.py
index bb918818cc70543fa14588214caab65c05af0bba..1c0f3fe29e146d89e8a283082422807bca2ab48c 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -856,11 +856,11 @@ def build_platform(fpga, firmware):
         dram_clk_freq = clk_freq
     if fpga == 'isim':
         clk_freq = 50e6 # below 50 mhz, stops DRAM being enabled
-        dram_clk_freq = clk_freq
-        #dram_clk_freq = 100e6
+        #dram_clk_freq = clk_freq
+        dram_clk_freq = 100e6
     if fpga == 'versa_ecp5':
-        clk_freq = 50e6 # crank right down to test hyperram
-        #dram_clk_freq = 100e6
+        clk_freq = 40e6 # crank right down to timing threshold
+        dram_clk_freq = 100e6
     if fpga == 'versa_ecp5_85':
         # 50MHz works.  100MHz works.  55MHz does NOT work.
         # Stick with multiples of 50MHz...
@@ -897,7 +897,7 @@ def build_platform(fpga, firmware):
 
     # get DDR resource pins, disable if clock frequency is below 50 mhz for now
     ddr_pins = None
-    if (clk_freq >= 50e6 and platform is not None and
+    if (dram_clk_freq >= 50e6 and platform is not None and
         fpga in ['versa_ecp5', 'versa_ecp5_85', 'arty_a7', 'isim']):
         ddr_pins = platform.request("ddr3", 0,
                                     dir={"dq":"-", "dqs":"-"},