update comments
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 19 May 2020 20:22:38 +0000 (21:22 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 19 May 2020 20:22:38 +0000 (21:22 +0100)
libreriscv
src/soc/fu/trap/pipe_data.py

index 6ce15b77d086f4f2d0b945b032fbaa2096f2ef6f..3e665eb7607d37b92567a445e795c4d7b6e00fc9 160000 (submodule)
@@ -1 +1 @@
-Subproject commit 6ce15b77d086f4f2d0b945b032fbaa2096f2ef6f
+Subproject commit 3e665eb7607d37b92567a445e795c4d7b6e00fc9
index 751a183583e6af7bbcf645c1c36b0f555b59bc86..581040c42c0828a41269738a25a3bbd2758f0a77 100644 (file)
@@ -26,10 +26,10 @@ class TrapInputData(IntegerData):
 class TrapOutputData(IntegerData):
     def __init__(self, pspec):
         super().__init__(pspec)
-        self.nia = Signal(64, reset_less=True) # RA
-        self.msr = Signal(64, reset_less=True) # RB/immediate
-        self.srr0 = Signal(64, reset_less=True) # RB/immediate
-        self.srr1 = Signal(64, reset_less=True) # RB/immediate
+        self.nia = Signal(64, reset_less=True) # NIA (Next PC)
+        self.msr = Signal(64, reset_less=True) # MSR
+        self.srr0 = Signal(64, reset_less=True) # SRR0 SPR
+        self.srr1 = Signal(64, reset_less=True) # SRR1 SPR
         self.should_trap = Signal(reset_less=True)
 
     def __iter__(self):