div probably uses ALU not Logical, needs double-checking though

diff --git a/src/soc/fu/div/pipe_data.py b/src/soc/fu/div/pipe_data.py
index e634a50567ee606d3d6ac65b1ecdfb2b834dc3ab..52ac0d92bd540c1de4338856984d74246960cd70 100644 (file)
--- a/src/soc/fu/div/pipe_data.py
+++ b/src/soc/fu/div/pipe_data.py
@@ -1,10 +1,10 @@
 from nmigen import Signal, Const
 from soc.fu.pipe_data import IntegerData
 from soc.fu.alu.pipe_data import ALUOutputData, CommonPipeSpec
-from soc.fu.logical.pipe_data import LogicalInputData
+from soc.fu.alu.pipe_data import ALUInputData # TODO: check this
 from soc.fu.logical.logical_input_record import CompLogicalOpSubset
 
 
 class DivPipeSpec(CommonPipeSpec):
-    regspec = (LogicalInputData.regspec, ALUOutputData.regspec)
+    regspec = (ALUInputData.regspec, ALUOutputData.regspec)
     opsubsetkls = CompLogicalOpSubset