self.rwid = rwid
self.alu = alu
+ self.counter = Signal(3)
self.go_rd_i = Signal(reset_less=True) # go read in
self.go_wr_i = Signal(reset_less=True) # go write in
self.issue_i = Signal(reset_less=True) # fn issue in
# outputs
m.d.comb += self.busy_o.eq(opc_l.q) # busy out
- m.d.comb += self.req_rel_o.eq(req_l.q & opc_l.q) # request release out
+
+ with m.If(self.go_rd_i):
+ m.d.sync += self.counter.eq(1)
+ with m.If(self.counter > 0):
+ m.d.sync += self.counter.eq(self.counter - 1)
+ with m.If(self.counter == 1):
+ m.d.comb += self.req_rel_o.eq(req_l.q & opc_l.q) # req release out
# create a latch/register for src1/src2
latchregister(m, self.src1_i, self.alu.a, src_l.q)
for i in range(len(dut.int_insn_i)):
yield dut.int_insn_i[i].eq(0)
yield
+ yield
+ yield
while True:
issue_o = yield dut.issue_o
if issue_o:
yield
+ yield
+ yield from print_reg(dut, [3,4,5])
+ yield
+ yield from print_reg(dut, [3,4,5])
yield
yield from print_reg(dut, [3,4,5])
yield
class Register(Elaboratable):
- def __init__(self, width, writethru=True):
+ def __init__(self, width, writethru=False):
self.width = width
self.writethru = writethru
self._rdports = []
for i in range(self.n_dests):
m.d.comb += self.xx_pend_o[i].eq(0) # initialise all array
m.d.comb += self.writable_o[i].eq(0) # to zero
+ m.d.comb += self.readable_o[i].eq(0) # to zero
# go_wr latch: reset on go_wr HI, set on issue
m.d.comb += wr_l.s.eq(self.issue_i)
# readable output signal
g_rd = Signal(self.reg_width, reset_less=True)
+ ro = Signal(reset_less=True)
m.d.comb += g_rd.eq((~self.g_wr_pend_i) & self.rd_pend_o)
- m.d.comb += self.readable_o.eq(g_rd.bool())
+ m.d.comb += ro.eq(g_rd.bool())
+ m.d.comb += self.readable_o.eq(ro)
# writable output signal
g_wr_v = Signal(self.reg_width, reset_less=True)
on a particular register (extremely unusual), they must set a Const
zero bit in the vector.
"""
- def __init__(self, dep, fu_vecs):
+ def __init__(self, dep, fu_vecs, sync=False):
self.reg_dep = dep
# inputs
self.fu_vecs = fu_vecs
+ self.sync = sync
for v in fu_vecs:
assert len(v) == dep, "FU Vector must be same width as regfile"
for v in self.fu_vecs:
vec_bit_l.append(v[i]) # fu bit for same register
pend_l.append(Cat(*vec_bit_l).bool()) # OR all bits for same reg
- m.d.comb += self.g_pend_o.eq(Cat(*pend_l)) # merge all OR'd bits
+ if self.sync:
+ m.d.sync += self.g_pend_o.eq(Cat(*pend_l)) # merge all OR'd bits
+ else:
+ m.d.comb += self.g_pend_o.eq(Cat(*pend_l)) # merge all OR'd bits
return m