# YOSYS_FLATTEN = Yes
CHIP = chip
- CORE = add
+ CORE = memory
MARGIN = 2
BOOMOPT = # -A
BOOGOPT =
# RM_CHIP = Yes
NETLISTS = $(shell cat nets.txt)
-# PATTERNS = add_r
+# PATTERNS = memory_r
include ./mk/design-flow.mk
-blif: add.blif
-vst: add.vst
+blif: memory.blif
+vst: memory.vst
lvx: lvx-chip_cts_r
druc: druc-chip_cts_r
view: cgt-chip_cts_r
-sim: asimut-add_cts_r
+sim: asimut-memory_cts_r
+++ /dev/null
-from nmigen import *
-from nmigen.cli import rtlil
-
-
-class ADD(Elaboratable):
- def __init__(self, width):
- self.a = Signal(width)
- self.b = Signal(width)
- self.f = Signal(width)
-
- def elaborate(self, platform):
- m = Module()
- m.d.sync += self.f.eq(self.a + self.b)
- return m
-
-
-def create_ilang(dut, ports, test_name):
- vl = rtlil.convert(dut, name=test_name, ports=ports)
- with open("%s.il" % test_name, "w") as f:
- f.write(vl)
-
-if __name__ == "__main__":
- alu = ADD(width=4)
- create_ilang(alu, [alu.a, alu.b, alu.f], "add")
--- /dev/null
+from nmigen import *
+from nmigen.cli import rtlil
+
+
+class ADD(Elaboratable):
+ def __init__(self, width):
+ self.a = Signal(width)
+ self.b = Signal(width)
+ self.f = Signal(width)
+
+ def elaborate(self, platform):
+ m = Module()
+ m.d.sync += self.f.eq(self.a + self.b)
+ #a = Signal(9)
+ #q = Signal(64)
+ #d = Signal(64)
+ #we = Signal(8)
+ #sram = Instance("SPBlock_512W64B8W", i_a=a, o_q=q, i_d=d, i_we=we)
+ #m.submodules += sram
+ return m
+
+
+def create_ilang(dut, ports, test_name):
+ vl = rtlil.convert(dut, name=test_name, ports=ports)
+ with open("%s.il" % test_name, "w") as f:
+ f.write(vl)
+
+if __name__ == "__main__":
+ alu = ADD(width=4)
+ create_ilang(alu, [alu.a, alu.b, alu.f], "memory")